參數(shù)資料
型號: M2006-04-622.0800LF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36
封裝: 9 X 9 MM, CERAMIC, LCC-36
文件頁數(shù): 10/12頁
文件大?。?/td> 417K
代理商: M2006-04-622.0800LF
M2006-04 Datasheet Rev 0.1
7 of 12
Revised 29Apr2003
M2006-04
VCSO BASED FREQUENCY TRANSLATOR
Preliminar y In f o r m atio n
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M2006-04 requires the use of an
external loop filter components. These are connected to
the provided filter pins (see Figure 5). Due to the
differential signal path design, the implementation
consists of two identical complementary RC filters as
shown in Figure 5, below.
PLL bandwidth is affected by the “M” value as well as
the VCSO frequency. See Table 8, External Loop Filter
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN
nOP_IN
External Loop Filter Component Values 1
M2006-04-622.080
VCSO Parameters: KVCO = 800kHz/V, VCSO Bandwidth = 70kHz
Device Configuration
Example External Loop
Filter Component Values
Nominal Performance Using
These Values
FRef
(MHz)
FPhase
Detector
(MHz)
FVCSO
(MHz)
M
Divider
Value
NBW
Pin
RIN R loop C loop R post C post PLL Loop
Bandwidth
Damping
Factor
Passband
Peaking
(dB)
19.44
622.08
32
0
50k
39
k
0.10F 20k 220pF
3.4k
Hz
4.4
0.1
1
2M
115
Hz
0.7
2.2
19.44
622.08
32
0
50k
150
k
0.10F 82k
15
pF
14k
Hz
16.77
0.001
1
2M
310
Hz
2.7
0.25
19.44
622.08
32
0
50k
910
10
F 100k 220pF
770
Hz
10
0.02
1
2M
20
Hz
1.6
0.5
155.52
622.08
4
0
50k
15
k
0.10F 100k 15pF
10k
Hz
4.7
0.1
1
2M
338
Hz
0.75
2.0
155.52
622.08
4
0
50k
2
k
10
F
50
k
220pF
1.4k
Hz
6.3
0.05
1
2M
40
Hz
1
1.25
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and
External Loop Filter Component Values determine
Loop Bandwidth, Damping Factor, and Passband
Peaking.
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