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參數(shù)資料
| 型號： | M2006-04-622.0800LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 417K |
| 代理商： | M2006-04-622.0800LF |
M2006-04 Datasheet Rev 0.1
5 of 12
Revised 29Apr2003
M2006-04
VCSO BASED FREQUENCY TRANSLATOR
Preliminar y In f o r m atio n
Serial Configuration Register
The M2006-04 is serially programmed by way of a
three-wire interface, with the inputs being S_DATA,
S_CLOCK
, and S_LOAD.
When S_LOAD is LOW, configuration data is serially
loaded from S_DATA into the Serial Configuration
Register (or “shift register”) with the rising edge of
S_CLOCK
. The T2 bit is loaded first, M0 last.
(See point “a” in the timing diagram:
“Figure 4, P Divider and Outputs,” below.)
The contents of the shift register are loaded in parallel
into the R and M dividers when S_LOAD transitions to
HIGH (at point “b” in the timing diagram.)
The divider values are “l(fā)atched” when S_LOAD transitions
to LOW again (at point “c” in the diagram). This means
the divider values remain loaded and unaffected by any
serial input.
(If S_LOAD is held HIGH, any S_DATA input is passed
directly to the R and M dividers on each rising edge of
S_CLOCK
.)
See also:
- Table 6, Serial Mode Function, below
Serial Programming Timing Diagram
Figure 4: Serial Programming Timing Diagram
Serial Mode Function
Pa L = Low; H = High; X = Don't care; = Rising Edge Transition; = Falling Edge Transition
S_LOAD S_CLOCK S_DATA Conditions
L
Data
Serial input mode. Shift register loads state of S_DATA on each rising clock of
S_CLOCK. (However, serial input does not affect the values in the R and M dividers.)
L
Data
Entire contents of the shift register are passed (in parallel) to the R and M dividers.
L
Data
R and M divider values are latched.
L
X
Serial input does not affect the values in the R and M dividers.
H
Data
Serial input affects dividers: S_DATA passed directly to R and M dividers as it is
clocked.
Table 6: Serial Mode Function
S_DATA
S_CLOCK
S_LOAD
a
b c
T2
T1
T0
R8
R7
R6
R5
R4
R3
R2
R1
R0
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
Points a, b, and c used in section “Serial Configuration Register” above.
T1 and T0, which are used for test automation, must be set to 0.
T2 is set to 1 for normal bandwidth, 0 for narrow bandwidth. (If either NBW pin or T2 is asserted, device goes into Narrow Bandwidth mode.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2006-04-625.0000 | 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Bulk 制造商:Integrated Device Technology Inc 功能描述:FREQUENCY TRANSLATOR |
| M2006-04-625.0000T | 功能描述:時鐘合成器/抖動清除器 FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| M2006099 | 制造商:TURCK Inc 功能描述:WIRE AND CABLE |
| M2006-11-622.0800 | 制造商:Ics 功能描述:PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), 36 Pin Ceramic LCC |
| M2006-12 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION |
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