參數(shù)資料
型號: M12S16161A
廠商: Electronic Theatre Controls, Inc.
英文描述: 512K x 16Bit x 2Banks Synchronous DRAM
中文描述: 為512k × 16Bit的X 2Banks同步DRAM
文件頁數(shù): 6/28頁
文件大?。?/td> 871K
代理商: M12S16161A
ESMT
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
M12S16161A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2005
Revision
:
1.0
6/28
-10
-15
Parameter
Symbol
Min
Max
Min
Max
Unit
Note
CAS Latency =3
10
15
CLK cycle time
CAS Latency =2
t
CC
15
1000
15
1000
ns
1
CAS Latency =3
-
9
-
12
CLK to valid
output delay
CAS Latency =2
t
SAC
-
12
-
12
ns
1
Output data hold time
t
OH
2.5
2.5
ns
2
CLK high pulse width
t
CH
3
3
ns
3
CLK low pulse width
t
CL
3
3
ns 3
Input setup time
t
SS
3
4
ns
3
Input hold time
t
SH
1
2
ns
3
CLK to output in Low-Z
t
SLZ
1
1
ns
2
CAS Latency =3
-
7
-
9
CAS Latency =2
-
8
-
9
CLK to output in
Hi-Z
CAS Latency =1
t
SHZ
-
-
-
24
ns
*All AC parameters are measured from half to half.
Note:
1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.
相關(guān)PDF資料
PDF描述
M12S16161A-10T 512K x 16Bit x 2Banks Synchronous DRAM
M12S16161A-10TG 512K x 16Bit x 2Banks Synchronous DRAM
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M12S16161A-15TG 512K x 16Bit x 2Banks Synchronous DRAM
M1300 Mini size of Discrete semiconductor elements
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