參數(shù)資料
型號: M12S16161A
廠商: Electronic Theatre Controls, Inc.
英文描述: 512K x 16Bit x 2Banks Synchronous DRAM
中文描述: 為512k × 16Bit的X 2Banks同步DRAM
文件頁數(shù): 14/28頁
文件大?。?/td> 871K
代理商: M12S16161A
ESMT
Read & Write Cycle at Same Bank @Burst Length = 4
M12S16161A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2005
Revision
:
1.0
14/28
*Note:
1.Minimum row cycle times is required to complete internal DRAM operation.
2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z(t
SHZ
) after the clock.
3.Access time from Row active command. tcc*(t
RCD
+CAS latency-1)+t
SAC
4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
t
RCD
t
RC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CS
RAS
CAS
ADDR
DQM
BA
CL=2
CL=3
Ra
Rb
Cb0
t
OH
t
SAC
t
SHZ
t
SHZ
t
RDL
Read
(A-Bank)
Row Active
Precharge
(A-Bank)
(A-Bank)
Precharge
(A-Bank)
Write
(A-Bank)
Row Active
(A-Bank)
*Note3
*Note3
*Note4
*Note4
: Don't care
*Note1
Qa0
Qa1
Qa2
Qa3
Db0
Db3
Db1
Db2
Qa0
Qa1
Qa2
Qa3
Db0
Db3
Db1
Db2
t
RAC
t
RAC
t
RDL
Ca0
A10/AP
Ra
Rb
HIGH
*Note2
WE
t
OH
t
SAC
QC
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