參數(shù)資料
型號: M12S16161A
廠商: Electronic Theatre Controls, Inc.
英文描述: 512K x 16Bit x 2Banks Synchronous DRAM
中文描述: 為512k × 16Bit的X 2Banks同步DRAM
文件頁數(shù): 23/28頁
文件大?。?/td> 871K
代理商: M12S16161A
ESMT
Burst Read Single bit Write Cycle @Burst Length=2
M12S16161A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Jun. 2005
Revision
:
1.0
23/28
*Note:1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length.
2.When BRSW write command with auto precharge is executed, keep it in mind that t
RAS
should not be violated.
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge
command will be issued after two clock cycles.
C L O C K
C K E
A D D R
CL=2
DQ M
A10/AP
BA
RAa
RAc
RAa
QAb0
Row Active
(A-Bank)
W rite
(A-Bank)
:Don't Car e
HIGH
QAb1
Precharge
(A- Bank)
CAa
RBb
CAb
CBc
CAd
RAc
DBc0
DQ
DAa0
QAb0
DBc0
QAb1
CL=3
Row Active
(B-Bank)
Row Active
(A- Bank)
W rite with
Auto Pr echarge
( B-Bank)
Read
( A- Bank)
DAa0
QAd0 QAd1
QAd0 QAd1
*Not e 1
CS
RAS
CAS
W E
RBb
*Not e 2
Read with
Auto Precharge
(A-Bank)
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