ESMT

Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page

M12S16161A

Elite Semiconductor Memory Technology Inc.

Publication Date

:

Jun. 2005

Revision

:

1.0

22/28

*Note:

1. Burst can’t end in full page mode, so auto precharge can’t issue.

2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by

AC parameter of t

RDL

.

DQM at write interrupted by precharge command is needed to prevent invalid write.

Input data after Row precharge cycle will be masked internally.

3.Burst stop is valid at every burst length.

C L O C K

C K E

A D D R

DQ

DQ M

A10/AP

RAa

CAa

CAb

RAa

DAa0 DAa1

DAb1

DAb0

DAb2

Row Active

(A-Bank)

W rite

(A-Bank)

Burst Stop

W rite

(A-Bank)

:Don't Car e

HIGH

DAa2 DAa3 DAa4

DAb3 DAb4 DAb5

Precharge

( A- Bank)

t

B D L

t

RD L

*Not e 2

CS

RAS

CAS

W E

BA

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19