參數(shù)資料
型號(hào)： M-ORT82G51BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁數(shù)： 58/94頁
文件大小： 2104K
代理商： M-ORT82G51BM680-DB
Lattice Semiconductor
ORCA ORT82G5 Data Sheet
61
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
The ORCA Series 4 FPSCs include circuitry designed to protect the chips from damaging substrate injection cur-
rents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed
during storage, handling, and use to avoid exposure to excessive electrical stress.
Recommended Operating Conditions
SERDES Electrical and Timing Characteristics
Table 21. Absolute Maximum Ratings
Table 22. Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Unit
Storage Temperature
TSTG
– 65
150
°C
Power Supply Voltage with Respect to Ground
VDD33
– 0.3
4.2
V
VDDIO
– 0.3
4.2
V
VDD15
—
2.0
V
Input Signal with Respect to Ground
VIN
VSS – 0.3
VDDIO + 0.3
V
Signal Applied to High-impedance Output
—
VSS – 0.3
VDDIO + 0.3
V
Maximum Package Body (Soldering) Temperature
—
220
°C
Parameter
Symbol
Min.
Max.
Unit
Power Supply Voltage with Respect to Ground
1
VDD33
3.0
3.6
V
VDD15
1.425
1.575
V
Input Voltages
VIN
VSS – 0.3
VDDIO + 0.3
V
Junction Temperature
2
TJ
– 40
125
°C
1. For FPGA Recommended Operating Conditions and Electrical Characteristics, see the Recommended Operating Conditions and Electri-
cal Characteristics tables in the ORCA Series 4 FPGA data sheet (OR4E04) and the ORCA Series 4 I/O Buffer Technical Note. FPSC
Standby Currents (IDDSB15 and IDDSB33) are tested with the Embedded Core in the powered down state.
2. Designed for greater than 10 year electromigration life at 3.125 Gbits/s at 100 C junction temperature.
Parameter
Conditions
Min.
Typ.
Max.
Unit
Power Dissipation SERDES, MUX/DEMUX, Align FIFO and I/O (per channel), 1.25 Gbit/s
—
195
mW
SERDES, MUX/DEMUX, Align FIFO and I/O (per channel), 2.50 Gbit/s
—
210
mW
SERDES, MUX/DEMUX, Align FIFO and I/O (per channel), 3.25 Gbit/s
—
225
mW
8b/10b Encoder/Decoder (per channel)
—
50
mW
Parameter
Conditions
Min.
Typ.
Max.
Unit
VDD15 Supply Voltage (VDD15, VDDRx, VDDTx, VDDAUX, VDDGB)
—
1.425
—
1.575
V
CML I/O Supply Voltage (VDDIB, VDDOB)
—
1.425
—
1.890
V
Note:VDDIB is the center tap of the CML input buffer. In some cases this signal may be left oating, or tied to another voltage level when not
interfacing to CML output buffers. See the SERDES CML Buffer Interface Application note for details.
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