參數(shù)資料
型號(hào)： M-ORT82G51BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁(yè)數(shù)： 21/94頁(yè)
文件大?。?/td> 2104K
代理商： M-ORT82G51BM680-DB
Lattice Semiconductor
ORCA ORT82G5 Data Sheet
28
XAUI Lane Alignment Function (Lane Deskew)
In XAUI mode, the receive section in each lane uses the /A/ code group to compensate for lane-to-lane skew. The
mechanism restores the timing relationship between the 4 lanes by lining up the /A/ characters into a column.
Figure 14 shows the alignment of four lanes based on /A/ character. A minimum spacing of 16 code-groups implies
that at least ± 80 bits of skew compensation capability should be provided, which the ORT82G5 signicantly
exceeds.
Figure 14. Deskew Lanes by Aligning /A/ Columns
Mixing Half-rate, Full-rate Modes
When channel alignment is enabled, all receive channels within an alignment group should be congured at the
same rate. For example, channels AA, AB, can be congured for twin alignment and full-rate mode, while channels
AC, AD that form an alignment group can be congured for half-rate mode. In quad alignment mode, each receive
quad can be congured in either half or full-rate mode.
When channel alignment is disabled within a quad, any receive channel within the quad can be used in half-rate or
full-rate mode. The clocking strategy for half-rate mode in both scenarios (channel alignment enabled or disabled)
is described in the section ORT82G5 Reference Clocks and Internal Clock Distribution later in this data sheet.
Multi-channel alignment conguration
Register settings for multi-channel alignment are shown in Table 6.
Table 6. Multichannel Alignment Modes
To align all eight channels:
FMPU_SYNMODE_A[A:D] = 11
FMPU_SYNMODE_B[A:D] = 11
To align all four channels in SERDES A:
FMPU_SYNMODE_A[A:D] = 01
To align two channels in SERDES A:
Register Bits
FMPU_SYNMODE_xx[0:1]
Mode
00
No multichannel alignment.
10
Twin channel alignment.
01
Quad channel alignment.
11
Eight channel alignment.
Note: Where xx is one of A[A:D] and B[A:D].
LANE 0
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 1
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 2
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 3
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 0
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 1
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 2
K
RR
K
R
K
R
K
R
K
RR
K
A
LANE 3
K
RR
K
R
K
R
K
R
K
RR
K
A
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