參數(shù)資料
型號： M-ORT82G51BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁數(shù)： 47/94頁
文件大?。?/td> 2104K
代理商： M-ORT82G51BM680-DB
Lattice Semiconductor
ORCA ORT82G5 Data Sheet
51
SERDES Common Transmit and Receive Channel Conguration Registers (Read/Write), xx=[AA, ...,BD]
30002 - AA
30012 - AB
30022 - AC
30032 - AD
30102 - BA
30112 - BB
30122 - BC
30132 - BD
[0]
TXHR_xx
00
Transmit Half Rate Selection Bit, Channel xx. When TXHR_xx = 1,
HDOUT_xx's baud rate = (REFCLK[A:B]*10) and TCK78[A:B] =(REF-
CLK[A:B]/4); when TXHR_xx=0, HDOUT_xx's baud rate = (REF-
CLK[A:B]*20) and TCK78[A:B]=(REFCLK[A:B]/2).
TXHR_xx = 0 on device reset.
[1]
PWRDNT_xx
Transmit Powerdown Control Bit, Channel xx. When PWRDNT_xx = 1,
sections of the transmit hardware are powered down to conserve power.
PWRDNT_xx = 0 on device reset.
[2]
PE0_xx
Transmit Preemphasis Selection Bit 0, Channel xx. PE0_xx and PE1_xx
select one of three preemphasis settings for the transmit section.
PEO_xx=PE1_xx = 0, Preemphasis is 0%
PEO_xx=1, PE1_xx = 0 or PEO_xx=0, PE1_xx = 1, Preemphasis is
12.5%
PEO_xx=PE1_xx = 1, Preemphasis is 25%.
PEO_xx=PE1_xx = 0 on device reset.
[3]
PE1_xx
[4]
HAMP_xx
Transmit Half Amplitude Selection Bit, Channel xx. When HAMP_xx = 1,
the transmit output buffer voltage swing is limited to half its normal ampli-
tude. Otherwise, the transmit output buffer maintains its full voltage
swing.
HAMP_xx = 0 on device reset.
[5]
Reserved
Reserved. Must be set to 0
Set to 0 on device reset.
[6]
Reserved
[7]
8b10bT_xx
Transmit 8b/10b Encoder Enable Bit, Channel xx. When 8b10bT_xx = 1,
the 8b/10b encoder in the transmit path is enabled. Otherwise, the data
is passed unencoded.
8b10bT_xx = 0 on device reset.
30003 - AA
30013 - AB
30023 - AC
30033 - AD
30103 - BA
30113 - BB
30123 - BC
30133 - BD
[0]
RXHR_xx
20
Receive Half Rate Selection Bit, Channel xx. When RXHR_xx =1,
HDIN_xx's baud rate = (REFCLK[A:B]*10) and RCK78[A:B]=(REF-
CLK[A:B]/4); when RXHR_xx=0, HDIN_xx's baud rate = (REF-
CLK[A:B]*20) and RCK78[A:B]=(REFCLK/2).
RXHR_xx = 0 on device reset.
[1]
PWRDNR_xx
Receiver Power Down Control Bit, Channel xx. When PWRDNR_xx = 1,
sections of the receive hardware are powered down to conserve power.
PWRDNR_xx = 0 on device reset.
[2]
Reserved
Reserved. Must be set to 1.
Set to 1 on device reset.
[3]
8b10bR_xx
Receive 8b/10b Decoder Enable Bit, Channel xx. When 8b10bR = 1, the
8b/10b decoder in the receive path is enabled. Otherwise, the data is
passed undeocded.
8b10bR_xx = 0 on device reset.
[4]
LINKSM_xx
Link State Machine Enable Bit, Channel xx. When LINKSM_xx = 1, the
receiver Fiber Channel link state machine is enabled. Otherwise, the
Fibre Channel link state machine is disabled.
NOTE: LINKSM_xx is ignored when XAUI_MODE_xx=1.
LINKSM_xx = 0 on device reset.
[5:7]
Not Used
Table 20. Memory Map (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
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