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參數(shù)資料
| 型號(hào)： | M-ORT82G51BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 22/94頁 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G51BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
29
FMPU_SYNMODE_A[A:B] = 10 for channel AA and AB
FMPU_SYNMODE_A[C:D] = 10 for channel AC and AD
A similar alignment can be dened for SERDES B.
To enable/disable synchronization signal of individual channel within a multi-channel alignment group:
FMPU_STR_EN_xx = 1 enabled
FMPU_STR_EN_xx = 0 disabled
where xx is one of A[A:D] and B[A:D].
To resynchronize a multichannel alignment group set the following bit to zero, and then set it to 1.
FMPU_RESYNC8 for eight channel A[A:D] and B[A:D]
FMPU_RESYNC4A for quad channel A[A:D]
FMPU_RESYNC2A1 for twin channel A[A:B]
FMPU_RESYNC2A2 for twin channel A[C:D]
FMPU_RESYNC4B for quad channel B[A:D]
FMPU_RESYNC2B1 for twin channel B[A:B]
FMPU_RESYNC2B2 for twin channel B[C:D]
To resynchronize an independent channel (resetting the write and the read pointer of the FIFO) set the following bit
to zero, and then set it to 1.
FMPU_RESYNC1_xx
A two-to-one multiplexer is used to select between aligned or nonaligned data to be sent to the FPGA on
MRWDxx[39:0]. The 40-bit MRWDxx[39:0] output format is shown in Table 4. and .
Alignment Sequence
1.
Follow steps 1 and 2 in the start up sequence described in a later section.
2.
Initiate a SERDES software reset by setting the SWRST bit to 1 and then to 0. Note that, any changes to the
SERDES conguration bits should be followed by a software reset.
3.
Wait for 3 ms. REFCLK should be toggling by this time. During this time, congure the following registers.
Set the following bits in registers 30820, 30920
XAUI_MODE_xx-set to 1 for XAUI mode or keep the default value of 0.
Enable channel alignment by setting FMPU_SYNMODE bits in registers 30811, 30911.
FMPU_SYNMODE_xx. Set to appropriate values for 2, 4, or 8 alignment based on Table 6.
Set RCLKSEL[A:B] and TCKSEL[A:B] bits in registers 30A00.
RCKSEL[A:B]-choose clock source for 78 MHz RCK78x (Table 12).
TCKSEL[A:B]-Choose clock source for 78 MHz TCK78x (Table 11).Send data on serial links. Monitor the follow-
ing status/alarm bits:
Monitor the following alarm bits in registers 30000, 30010, 30020, 30030, 30100, 30110, 30120, 30130.
LKI-PLL_xx lock indicator. A 1 indicates that PLL has achieved lock.
Monitor the following status bits in registers 30804, 30904
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