參數(shù)資料
型號: M-ORT82G51BM680-DB
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
英文描述: FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝: PLASTIC, FBGA-680
文件頁數(shù): 55/94頁
文件大?。?/td> 2104K
代理商: M-ORT82G51BM680-DB
Lattice Semiconductor
ORCA ORT82G5 Data Sheet
59
Recommended Board-level Clocking for the ORT82G5
Option 1: Asynchronous Reference Clocks Between Rx and Tx Devices
Each board that uses the ORT82G5 as a transmit or receive device will have its own local reference clock as shown
in Figure 29. Figure 29 shows the ORT82G5 device on the switch card receiving data on two of its channels from a
separate source. Data tx1 is transmitted from a tx device with refclk1 as the reference clock and Data tx2 is trans-
mitted from a tx device with refclk2 as the reference clock. Receive channel AA locks to the incoming data tx1 and
receive channel AB locks to the incoming data tx2.
The advantage of this clocking scheme is the fact that it is not necessary to distribute a reference clock (typically
156 MHz for 10GE and 155.52 MHz for OC-192 applications) across a backplane.
Figure 29. Asynchronous Clocking Between Rx and Tx Devices
Option 2: Synchronous Reference Clocks to Rx and Tx Devices
In this type of clocking, a single reference clock is distributed to all receive and transmit devices in a system
(Figure 30). This distributed clocking scheme will permit maximum exibility in the usage of transmit and receive
channels in the current silicon such as:
All transmit and receive channels can be used within any quad in receive channel alignment or alignment bypass
mode.
In channel alignment mode, each receive channel operates on its own independent clock domain.
The disadvantage with this scheme is the fact that it is difcult to distribute a 156 MHz reference clock across a
backplane. This may require expensive clock driver chips on the board to drive clocks to different destinations
within the specied jitter limits for the reference clock.
REFCLK 1
PORT CARD #1
ORT82G5
PORT CARD #2
TX1
TX2
BACKPLANE
AA
AB
ORT82G5
SWITCH
ORT82G5
CARD
REFCLK 2
REFCLK 3
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