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參數(shù)資料
| 型號： | LU5X31F |
| 廠商： | Lineage Power |
| 英文描述： | Gigabit Ethernet Transceiver(千兆位以太網收發(fā)器) |
| 中文描述： | 千兆以太網收發(fā)器（千兆位以太網收發(fā)器） |
| 文件頁數(shù)： | 4/22頁 |
| 文件大?。?/td> | 348K |
| 代理商： | LU5X31F |
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Lucent Technologies Inc.
LU5X31F
Gigabit Ethernet Transceiver
Preliminary Data Sheet
August 2000
Functional Description
(continued)
Byte Alignment
When ENCDET = 1, the LU5X31F recognizes the
comma character and aligns this 10-bit character to the
word boundary, bits RX[0:9].
COMDET = 1 when the parallel output word contains a
byte-aligned comma character. The COMDET flag will
continue to pulse a logic 1 whenever a byte-aligned
comma character is at the parallel output port, indepen-
dent of ENCDET. When ENCDET = 0 there are two pos-
sible scenarios, depending upon when the comma
character is received:
1. If byte alignment had been previously achieved when
ENCDET had been a logic 1, the COMDET flag will
continue to pulse a logic 1 whenever a byte-aligned
comma character is at the parallel output port. If a
comma character occurs that is not on the word
boundary, no attempt will be made to align this
comma character, and the COMDET flag will remain
at a logic 0.
2. If byte alignment had
not
been previously achieved
when ENCDET had been a logic 1, then the first (and
only the first) comma character received will be
aligned to the word boundary. COMDET will pulse
when the comma character is aligned to the word
boundary.
Parallel Output Port
Timing for the parallel output data and the 62.5 MHz
receive-byte clock is given in Table 14.
Two low data-rate, receive-byte clocks are available as
outputs during use of the parallel output port in 10-bit
mode. RXCLK1 is the receive-byte clock used by the
protocol device to register bytes 0 and 2. RXCLK0 is
the receive-byte clock used by the protocol device to
register bytes 1 and 3, and it is 180 degrees out of
phase with RXCLK1. Both RXCLK1 and RXCLK0 can
be stretched during byte alignment, but not truncated
or slivered. The maximum allowable frequency of these
two clocks under all circumstances, excluding start-up,
will not exceed 80 MHz. The start-up time is specified
as 1 ms.
Loopback Mode Operation
A control signal input, EWRAP selects between two
possible sets of inputs: normal data (HDINP HDINN),
or internal loopback data. When EWRAP = 1, the serial
output ports, HDOUTP and HDOUTN, remain active.
The serial transmit data prior to the PECL output driver
is directed to the data recovery circuit, where the clock
is recovered and data is resynchronized to the recov-
ered clock. Retimed data and clock then go to the
serial-to-parallel converter.
Table 1. Definition of Bit Transmission/Reception Order
Serial Transmit/
Receive Rate
1.0 Gbits/s to 1.25 Gbits/s TX[0] bit serially transmitted first at
HDOUTP HDOUTN.
TX[9:0]
RX[9:0]
RX[0] bit received first at serial inputs,
HDINP HDINN.
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