參數(shù)資料
型號(hào)： LU5X31F
廠商： Lineage Power
英文描述： Gigabit Ethernet Transceiver(千兆位以太網(wǎng)收發(fā)器)
中文描述： 千兆以太網(wǎng)收發(fā)器（千兆位以太網(wǎng)收發(fā)器）
文件頁(yè)數(shù)： 3/22頁(yè)
文件大?。?/td> 348K
代理商： LU5X31F
3
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
LU5X31F
Gigabit Ethernet Transceiver
Functional Description
The LU5X31F transceiver provides for data transmis-
sion over fiber or coaxial media at 1.0 Gbits/s to
1.25 Gbits/s. The block diagram of a single channel is
shown in Figure 1. The input/output designations are
given in Table 3.
Transmitter Section
The transmitter accepts 8B/10B encoded bits in 10-bit
parallel form and converts to serial format for up
to 1.25 Gbits/s transmission. The serial nonreturn to
zero (NRZ) bits are shifted out of the device at a maxi-
mum rate of 1.25 Gbits/s. Internally, the device uses
two parallel shift registers that operate at half rate (i.e.,
a maximum of 625 MHz) for reduced power consump-
tion. The two shift registers drive the PECL output
buffer in an interleaved manner to construct the
1.25 Gbits/s output data stream.
The typical transmit and receive high-speed I/O inter-
facing is shown in Figures 8 and 9, for a single-channel
application.
The transmit shift register and other circuits are driven
with clocks generated from a 500 MHz—625 MHz inter-
nal clock. This internal clock is sourced from a voltage-
controlled oscillator (VCO) that is locked to the external
reference of 100 MHz—125 MHz. The internal transmit
phase-lock loop multiplies the frequency of the input
reference clock by a factor of 5, and controls the trans-
mit jitter bandwidth with appropriate design of the jitter
transfer function. The transmit phase-lock loop gener-
ates multiple clock phases that are all used by each of
the four receiver circuits. The clock phases are derived
from the transmit VCO.
Receiver Section
The receiver circuit extracts the clock from, and
retimes, the serial input data. The data is input to the
receiver on differential PECL buffers. External termina-
tion resistors are supplied by the user in accordance
with ANSIstandard, X3T11. The serial differential
inputs, HDINP and HDINN, are ac-coupled to the
device and internally biased to the PECL input com-
mon-mode range center. See Figures 8 and 9 for the
typical termination of the transmission lines.
The receiver data retiming circuit uses a digital timing
recovery loop that compares the phase of the input
data to multiple phases of the on-device VCO in the
transmit section. One of the phases is chosen to retime
the receive data. A digital low-pass filter is used in the
timing recovery loop to reject jitter from the data input.
A novel phase interpolation circuit permits the retiming
clock’s phase to be stepped with fine resolution for pre-
cise alignment of the sampling clock within the data
eye. Use of this digital data locking scheme avoids the
use of multiple analog phase-lock loops on-device that
can potentially injection lock to one another when
expanded to multiple receivers. Additionally, the digital
data locking loop maintains precise loop dynamics,
hence, the jitter transfer function is process and tem-
perature independent
.
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