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參數(shù)資料
| 型號(hào)： | LU5X31F |
| 廠商： | Lineage Power |
| 英文描述： | Gigabit Ethernet Transceiver(千兆位以太網(wǎng)收發(fā)器) |
| 中文描述： | 千兆以太網(wǎng)收發(fā)器（千兆位以太網(wǎng)收發(fā)器） |
| 文件頁數(shù)： | 17/22頁 |
| 文件大小： | 348K |
| 代理商： | LU5X31F |
17
Lucent Technologies Inc.
Preliminary Data Sheet
August 2000
LU5X31F
Gigabit Ethernet Transceiver
Test Modes
Note:
Test modes are intended for manufacture test only and are not guaranteed to be operational. They may be
modified or eliminated without prior notice.
The device has per-channel test modes as well as global test modes. The bypass PLL, BYPPLL, is a global test
input because it modifies the operation of the analog PLL. Test bits TEST[4:1] generally operate in the localized
mode. The LDST[A:D] inputs are enable signals that permit the TEST[4:1] signals to be injected into a particular
channel.
For example, if LDST = 1, the TEST[4:1] signals directly control the test modes in the A channel. Once LDST = 0,
the previous values of TEST[4:1] are held for the A channel. The TEST[4:1] signals control the four channels (A, B,
C, D) via level-sense latches that are gated with the LDST[A:D] inputs. TEST[5] is a global test pin used for both
injection of signals as well as for monitoring points within the device.
Table 16. Test Modes
Global
Local Test Configuration
Global
Operation
BYPPLL
0
0
TEST1
0
0
TEST2
0
0
TEST3
0
0
TEST4
1
0
TEST5
X
Output
Normal operation.
Analog PLL feedback signal viewed at
TEST5 pin.
Transceiver operates normally except
RX[9:0] output is from digital filter, not
the serial data.
Transceiver operates normally except
RX[9:0] output is from digital filter and
the analog PLL feedback signal is
viewed at TEST5 pin.
Digital filter forced to count. Pulses
applied at TEST4 increment accumula-
tor; pulses at TEST5 decrement accu-
mulator.
RX[9:0] output is from digital filter, not
the serial data. Digital filter forced to
count. Pulses applied at TEST4 incre-
ment accumulator; pulses at TEST5
decrement accumulator.
Parallel loopback. TX[9:0] = RX[9:0].
RX[9:0] remains active.
Parallel loopback. TX[9:0] = RX[9:0]
and analog PLL feedback signal viewed
at TEST5 pin. RX[9:0] remains active.
RX[9:0] output is from digital filter, not
the serial data. Receive channel is held
in reset. BYPPLL overrides this reset.
RX[9:0] output is from digital filter, not
the serial data. Receive channel is held
in reset. BYPPLL overrides this reset.
Analog PLL feedback signal viewed at
TEST5 pin.
Transmitter is held in reset. BYPPLL
overrides this reset.
0
0
0
1
1
X
0
0
0
1
0
Output
0
0
1
0
P
P
0
0
1
1
P
P
0
1
0
0
1
X
0
1
0
0
0
Output
0
1
0
1
1
X
0
1
0
1
0
Output
0
1
1
0
1
X
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