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參數(shù)資料
| 型號： | LTC6946IUFD-3#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTEGER-N PLL W/VCO 28QFN |
| 軟件下載： | PLLWizard™ PLLWizard™, with .NET 2.0 installer |
| 標準包裝： | 2,500 |
| 類型： | 時鐘/頻率合成器（RF/IF），分數(shù)-N，整數(shù)-N， |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 5.79GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-QFN（4x5） |
| 包裝： | 帶卷 (TR) |
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LTC6946
17
6946fa
OPERATION
SERIAL PORT
The SPI-compatible serial port provides control and
monitoring functionality. A configurable status output,
STAT, gives additional instant monitoring.
Communication Sequence
The serial bus is comprised of CS, SCLK, SDI and SDO.
Data transfers to the part are accomplished by the serial bus
master device first taking CS low to enable the LTC6946’s
port. Input data applied on SDI is clocked on the rising edge
of SCLK, with all transfers MSB first. The communication
burst is terminated by the serial bus master returning CS
high. See Figure 7 for details.
Data is read from the part during a communication burst
using SDO. Readback may be multidrop (more than one
LTC6946 connected in parallel on the serial bus), as SDO
is three-stated (Hi-Z) when CS = 1, or when data is not
being read from the part. If the LTC6946 is not used in
a multidrop configuration, or if the serial port master is
not capable of setting the SDO line level between read
sequences, it is recommended to attach a high value
resistor of greater than 200k between SDO and GND to
ensure the line returns to a known level during Hi-Z states.
See Figure 8 for details.
Single Byte Transfers
The serial port is arranged as a simple memory map, with
status and control available in 12, byte-wide registers. All
data bursts are comprised of at least two bytes. The 7 most
significant bits of the first byte are the register address,
with an LSB of 1 indicating a read from the part, and LSB
of 0 indicating a write to the part. The subsequent byte,
or bytes, is data from/to the specified register address.
See Figure 9 for an example of a detailed write sequence,
and Figure 10 for a read sequence.
Figure 11 shows an example of two write communication
bursts. The first byte of the first burst sent from the serial
bus master on SDI contains the destination register address
(Addr0) and an LSB of “0” indicating a write. The next byte
is the data intended for the register at address Addr0. CS is
then taken high to terminate the transfer. The first byte of
the second burst contains the destination register address
(Addr1) and an LSB indicating a write. The next byte on
SDI is the data intended for the register at address Addr1.
CS is then taken high to terminate the transfer.
MASTER–CS
MASTER–SCLK
tCSS
tCS
tCH
DATA
6946 F07
tCKL
tCKH
tCSS
tCSH
MASTER–SDI
MASTER–CS
MASTER–SCLK
LTC6946–SDO
Hi-Z
6946 F08
8TH CLOCK
DATA
tDO
Figure 7. Serial Port Write Timing Diagram
Figure 8. Serial Port Read Timing Diagram
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