參數(shù)資料
型號(hào)： LTC6946IUFD-3#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 19/30頁(yè)
文件大?。?/td> 0K
描述： IC INTEGER-N PLL W/VCO 28QFN
軟件下載： PLLWizard™
PLLWizard™, with .NET 2.0 installer
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 時(shí)鐘/頻率合成器（RF/IF），分?jǐn)?shù)-N，整數(shù)-N，
PLL： 是
輸入： 時(shí)鐘
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 5.79GHz
除法器/乘法器： 是/是
電源電壓： 3.15 V ~ 5.25 V
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 28-QFN（4x5）
包裝： 帶卷 (TR)
LTC6946
26
6946fa
Figure 18. Example SMT Balun Connection
Figure 19. Example TL Balun Connection
APPLICATIONS INFORMATION
SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES
Care must be taken when creating a PCB layout to mini-
mize power supply decoupling and ground inductances.
All power supply V+ pins should be bypassed directly to
the ground plane using a 0.1μF ceramic capacitor as close
to the pin as possible. Multiple vias to the ground plane
should be used for all ground connections, including to
the power supply decoupling capacitors.
The package’s exposed pad is a ground connection, and
must be soldered directly to the PCB land. The PCB land
pattern should have multiple thermal vias to the ground
plane for both low ground inductance and also low thermal
resistance (see Figure 20 for an example). See QFN Pack-
age Users Guide, page 8, on Linear Technology website’s
Packaging Information page for specific recommendations
concerning land patterns and land via solder masks. A link
is provided below.
http://www.linear.com/designtools/packaging/index.jsp
Figure 20. Example Exposed Pad Land Pattern
REFERENCE SIGNAL ROUTING, SPURIOUS AND
PHASE NOISE
The charge pump operates at the PFD’s comparison
frequency fPFD. The resultant output spurious energy is
small and is further reduced by the loop filter before it
modulates the VCO frequency.
However, improper PCB layout can degrade the LTC6946’s
inherent spurious performance. Care must be taken to
prevent the reference signal fREF from coupling onto the
VCO’s tune line, or into other loop filter signals. Example
suggestions are the following.
1. Do not share power supply decoupling capacitors
between same voltage power supply pins.
2. Use separate ground vias for each power supply de-
coupling capacitor, especially those connected to VREF+,
VCP+, and VVCO+.
3. Physically separate the reference frequency signal from
the loop filter and VCO.
4. Do not place a trace between the CMA, CMB and CMC
pads underneath the package as worse phase noise
could result.
LTC6946
VRF
+
RF–
RF+
TO 50Ω
LOAD
6946 F18
12
BALUN
2
3
1
5
4
6
11
BALUN PIN CONFIGURATION
1
2
3
4
5
6
UNBALANCED PORT
GND OR DC FEED
BALANCED PORT
GND
NC
LTC6946
VRF
+
RF–
RF+
TO 50Ω
LOAD
PRI
SEC
6946 F19
12
11
6946 F20
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