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參數(shù)資料
| 型號： | LTC6946IUFD-3#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/30頁 |
| 文件大小： | 0K |
| 描述： | IC INTEGER-N PLL W/VCO 28QFN |
| 軟件下載： | PLLWizard™ PLLWizard™, with .NET 2.0 installer |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/頻率合成器（RF/IF），分?jǐn)?shù)-N，整數(shù)-N， |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 5.79GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-QFN（4x5） |
| 包裝： | 帶卷 (TR) |
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LTC6946
14
6946fa
OPERATION
Table 3. LKWIN[1:0] Programming
LKWIN[1:0]
tLWW
fPFD
0
3ns
>5MHz
1
10ns
≤5MHz
2
30ns
≤1.7MHz
3
90ns
≤550kHz
The PFD phase difference must be less than tLWW for the
LOKCNT number of successive counts before the lock
indicator asserts the LOCK flag. The LKCNT[1:0] bits found
in register h09 are used to set LOKCNT depending upon
the application. See Table 4 for LKCNT[1:0] programming
and the Applications Information section for examples.
Table 4. LKCNT[1:0] Programming
LKCNT[1:0]
COUNTS
032
1
128
2
512
3
2048
When the PFD phase difference is greater than tLWW, the
lock indicator immediately asserts the UNLOCK status
flag and clears the LOCK flag, indicating an out-of-lock
condition. The UNLOCK flag is immediately de-asserted
when the phase difference is less than tLWW. See Figure 4
for more details.
CHARGE PUMP
The charge pump, controlled by the PFD, forces sink
(DOWN) or source (UP) current pulses onto the CP pin,
which should be connected to an appropriate loop filter. See
Figure 5 for a simplified schematic of the charge pump.
The output current magnitude ICPmaybesetfrom250μAto
11.2mA using the CP[3:0] bits found in serial port register
h09. A larger ICP can result in lower in-band noise due to
the lower impedance of the loop filter components. See
Table 5 for programming specifics and the Applications
Information section for loop filter examples.
Table 5. CP[3:0] Programming
CP[3:0]
ICP
0
250μA
1
350μA
2
500μA
3
700μA
4
1.0mA
5
1.4mA
6
2.0mA
7
2.8mA
8
4.0mA
9
5.6mA
10
8.0mA
11
11.2mA
12 to 15
Invalid
The CPINV bit found in register h0A should be set for
applications requiring signal inversion from the PFD,
such as for complex external loops using an inverting op
amp. A passive loop filter as shown in Figure 14 requires
CPINV = 0.
+tLWW
–tLWW
UNLOCK FLAG
LOCK FLAG
t = COUNTS/fPFD
6946 F04
0
PHASE
DIFFERENCE
AT PFD
Figure 4. UNLOCK and LOCK Timing
25
+
–
+
–
CP
THI
0.9V
VCP
+
VCP
+
TLO
+
–
0.9V
6946 F05
+
–
VCP
+/2
CPMID
CPUP
UP
CPDN
DOWN
Figure 5. Simplified Charge Pump Schematic
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