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參數(shù)資料
| 型號： | LTC6946IUFD-3#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTEGER-N PLL W/VCO 28QFN |
| 軟件下載： | PLLWizard™ PLLWizard™, with .NET 2.0 installer |
| 標準包裝： | 2,500 |
| 類型： | 時鐘/頻率合成器（RF/IF），分數(shù)-N，整數(shù)-N， |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 5.79GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-QFN（4x5） |
| 包裝： | 帶卷 (TR) |
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LTC6946
10
6946fa
PIN FUNCTIONS
VREFO+ (Pin 1): 3.15V to 3.45V Positive Supply Pin for
REFO Circuitry. This pin should be bypassed directly to
the ground plane using a 0.1μF ceramic capacitor as close
to the pin as possible.
REFO (Pin 2): Reference Frequency Output. This produces
a low noise square wave, buffered from the REF± differential
inputs. The output is self-biased and must be AC-coupled
with a 22nF capacitor.
STAT (Pin 3): Status Output. This signal is a configurable
logical OR combination of the UNLOK, LOK, ALCHI, ALCLO,
THI and TLO status bits, programmable via the STATUS
register. See the Operation section for more details.
CS (Pin 4): Serial Port Chip Select. This CMOS input initi-
ates a serial port communication burst when driven low,
ending the burst when driven back high. See the Operation
section for more details.
SCLK (Pin 5): Serial Port Clock. This CMOS input clocks
serial port input data on its rising edge. See the Operation
section for more details.
SDI (Pin 6): Serial Port Data Input. The serial port uses
this CMOS input for data. See the Operation section for
more details.
SDO (Pin 7): Serial Port Data Output. This CMOS three-
state output presents data from the serial port during a
read communication burst. Optionally attach a resistor
of >200k to GND to prevent a floating output. See the
Operation section for more details.
VD
+ (Pin 8): 3.15V to 3.45V Positive Supply Pin for Serial
Port Circuitry. This pin should be bypassed directly to the
ground plane using a 0.1μF ceramic capacitor as close to
the pin as possible.
MUTE (Pin 9): RF Mute. The CMOS active-low input mutes
the RF± differential outputs while maintaining internal bias
levels for quick response to de-assertion.
GND (Pins 10, 17, 21): Negative Power Supply (Ground).
These pins should be tied directly to the ground plane with
multiple vias for each pin.
RF–, RF+ (Pins 11, 12):
RF Output Signals. The VCO
output divider is buffered and presented differentially on
these pins. The outputs are open collector, with 136Ω
(typical) pull-up resistors tied to VRF+ to aid impedance
matching. If used single ended, the unused output should
be terminated to 50Ω. See the Applications Information
section for more details on impedance matching.
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