參數(shù)資料
型號(hào)： LTC6946IUFD-3#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 13/30頁(yè)
文件大?。?/td> 0K
描述： IC INTEGER-N PLL W/VCO 28QFN
軟件下載： PLLWizard™
PLLWizard™, with .NET 2.0 installer
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 時(shí)鐘/頻率合成器（RF/IF），分?jǐn)?shù)-N，整數(shù)-N，
PLL： 是
輸入： 時(shí)鐘
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 5.79GHz
除法器/乘法器： 是/是
電源電壓： 3.15 V ~ 5.25 V
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 28-QFN（4x5）
包裝： 帶卷 (TR)
LTC6946
20
6946fa
OPERATION
STAT Output
The STAT output pin is configured with the x[5:0] bits
of register h01. These bits are used to bit-wise mask, or
enable, the corresponding status flags of status register
h00, according to Equation 2. The result of this bit-wise
Boolean operation is then output on the STAT pin:
STAT = OR (Reg00[5:0] AND Reg01[5:0])
(2)
or expanded:
STAT = (UNLOCK AND x[5]) OR
(ALCHI AND x[4]) OR
(ALCLO AND x[3]) OR
(LOCK AND x[2]) OR
(THI AND x[1]) OR
(TLO AND x[0])
For example, if the application requires STAT to go high
whenever the ALCHI, ALCLO, or THI flags are set, then
x[4], x[3], and x[1] should be set to “1”, giving a register
value of h1A.
Block Power-Down Control
The LTC6946’s power-down control bits are located in
register h02, described in Table 11. Different portions of
the device may be powered down independently. Care must
be taken with the LSB of the register, the POR (power-on
reset) bit. When written to a “1”, this bit forces a full reset of
the part’s digital circuitry to its power-up default state.
Table 11. Serial Port Register Bit Field Summary
BITS
DESCRIPTION
DEFAULT
ALCCAL
Auto Enable ALC During CAL Operation
1
ALCEN
Always Enable ALC (Override)
1
ALCHI
ALC Too Hi Flag
ALCLO
ALC Too Low Flag
ALCMON
Enable ALC Monitor for Status Flags Only
0
ALCULOK
Enable ALC When PLL Unlocked
0
BD[3:0]
Calibration B Divider Value
h3
BST
REF Buffer Boost Current
1
CAL
Start VCO Calibration (auto clears)
0
CP[3:0]
CP Output Current
hB
CPCHI
CP Enable Hi Voltage Output Clamp
1
CPCLO
CP Enable Low Voltage Output Clamp
1
CPDN
CP Pump Down Only
0
CPINV
CP Invert Phase
0
CPMID
CP Bias to Mid-Rail
1
CPRST
CP Three-State
1
CPUP
CP Pump Up Only
0
CPWIDE
CP Extend Pulse Width
0
FILT[1:0]
REF Input Buffer Filter
h3
LKCT[1:0]
PLL Lock Cycle Count
h1
LKEN
PLL Lock Indicator Enable
1
LKWIN[1:0] PLL Lock Indicator Window
h2
LOCK
PLL Lock Indicator Flag
MTCAL
Mutes Output During Calibration
1
ND[15:0]
N Divider Value (ND[15:0] > 31)
h00FA
OD[2:0]
Output Divider Value (0 < OD[2:0] < 7)
h1
OMUTE
Mutes RF Output
1
PART[4:0]
Part code (h01 for LTC6946-1, h02 for
LTC6946-2, h03 for LTC6946-3 Version)
h01, h02, h03
PDALL
Full Chip Power Down
0
PDOUT
Powers Down O_DIV, RF Output Buffer
0
PDPLL
Powers Down REF, REFO, R_DIV, PFD,
CPUMP, N_DIV
0
PDREFO
Powers Down REFO
1
PDVCO
Powers Down VCO, N_DIV
0
POR
Force Power-On Reset
0
RD[9:0]
R Divider Value (RD[9:0] > 0)
h001
REV[2:0]
Rev Code
h2
RFO[1:0]
RF Output Power
h3
THI
CP Clamp High Flag
TLO
CP Clamp Low Flag
UNLOK
PLL Unlock Flag
x[5:0]
STAT Output OR Mask
h04
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