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參數(shù)資料
| 型號： | LPC3240FET296 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARM926EJ-S with 256 kB SRAM, USB High-speed OTG, SD-MMC, NAND flash controller, Ethernet |
| 中文描述： | 32-BIT, FLASH, 266 MHz, RISC MICROCONTROLLER, PBGA296 |
| 封裝： | 15 X 15 MM, 0.70 MM PITCH, PLASTIC, MO-216, SOT1048-1, TFBGA-296 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 121K |
| 代理商： | LPC3240FET296 |
ES_LPC3240
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 9 — 1 June 2011
9 of 17
NXP Semiconductors
ES_LPC3240
Errata sheet LPC3240
Problem:
For DDR writes the LPC3240 drives the EMC_DQS[1:0] earlier in the data valid window
than center aligned. With the EMC_CLK at 133 MHz this produces a minimum set-up time
between the EMC_D[15:0] and EMC_DQS[1:0] of 600 ps across silicon process, voltage
and temperature. Test conditions are with the EMC buffers set to fast slew rate driving
2 inches of 50
transmission line and 10 pF load capacitance. DDR memories specify
EMC_D[15:0] to EMC_DQS[1:0] set-up time minimum as 400 ps. This leaves 200 ps
set-up time margin due to customer specific load and PCB layout implementation. See the
LPC3220_30_40_50 data sheet for the complete range of DDR data output set-up time,
t
su(Q)
, and data output hold time t
h(Q)
times.
Work-around:
To get the most DDR set-up time margin, the following is recommended:
1. The DDR initialization software should set the SDRAMCLK_CTRL register (0x4000
4068) SDRAM_PIN_SPEED[3:1] bits = 0 (fast slew rate). This is for both 1.8 V mobile
and 2.5 V DDR memories.
2. Systems requiring 128 MB or less of DDR should be implemented using a single
EMC_DYCSx_N for DDR. The single chip select system may be constructed with a
single 16-bit wide DDR or two 8-bit wide DDR SDRAMs using up to the maximum
supported 512 Mbit DDR density. Using two 8-bit wide DDRs will have less capacitive
loading and facilitate simple point-to-point routing of EMC_D[15:0] and
EMC_DQS[1:0] signals over using two 16-bit DDRs and two EMC_DYCSx banks.
3. Series termination resistors are not needed for the LPC3240 EMC outputs. If series
termination resistors are used they should be placed as close to the DDR
EMC_D[15:0] and EMC_DQS[1:0] pins as possible.
4. If the data bus EMC_D[15:0] is shared with additional devices (i.e., NOR flash,
buffers, etc.) the board should be routed with a daisy chain topology, where the
LPC3240 is placed at one extreme of the data bus and the DDR(s) at the other
extreme. Other device(s) should be placed between the LPC3240 and DDR memory
(closer to the DDR).
Fig 4.
Basic DDR write timing
command
EMC_D[15:0],
EMC_DQM[1:0]
t
DQSL
t
DQSH
t
DQSS
t
h(Q)
EMC_DQS[1:0]
EMC_CLK
002aae437
WRITE
t
su(Q)
t
DSH
t
DSS
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LPC3240FET296,551 | 功能描述:ARM微控制器 - MCU ARM9 256KRAM VFP USB OTG ETH RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LPC3240FET296/01 | 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 266MHZ, TFBGA-296 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 266MHZ, TFBGA-296, Controller Family/Series:LPC3200, Core Size 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 266MHZ, TFBGA-296, Controller Family/Series:LPC3200, Core Size:16bit / 32bit, No. of I/O's:87, Supply Voltage Min:2.7V, Supply Voltage Max:3.6V, Digital IC Case Style:TFBGA, No. of Pins:296, Program Memory Size:-, |
| LPC3240FET296/01,5 | 功能描述:ARM微控制器 - MCU ARM9 VFP USB OTG Improved LCD RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LPC3240FET296/01,551 | 制造商:NXP Semiconductors 功能描述:0 |
| LPC3240FET296/015 | 制造商:NXP Semiconductors 功能描述:LPC3240FET296/TFBGA296/TRAYBDP |
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