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參數(shù)資料
| 型號： | LPC3240FET296 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARM926EJ-S with 256 kB SRAM, USB High-speed OTG, SD-MMC, NAND flash controller, Ethernet |
| 中文描述： | 32-BIT, FLASH, 266 MHz, RISC MICROCONTROLLER, PBGA296 |
| 封裝： | 15 X 15 MM, 0.70 MM PITCH, PLASTIC, MO-216, SOT1048-1, TFBGA-296 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 121K |
| 代理商： | LPC3240FET296 |
ES_LPC3240
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 9 — 1 June 2011
3 of 17
NXP Semiconductors
ES_LPC3240
Errata sheet LPC3240
1. Product identification
The LPC3240 devices typically have the following top-side marking:
LPC3240FET296
xxxxxxx
xxYYWWR
The last letter in the last line (field ‘R’) will identify the device revision. This Errata Sheet
covers the following revisions of the LPC3240:
Table 1.
Revision identifier (R)
‘A’
[1]
‘-’
[2]
[1]
Revision ‘A’ parts with and without the /01 suffix are identical. For example, LPC3240FET296 Revision ‘A’ is
identical to LPC3240FET296/01 Revision ‘A’.
[2]
Does not apply to /01 parts.
Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the
device was manufactured during that year.
2. Errata overview
Device revision table
Revision description
Second device revision
Initial device revision
Table 2.
Functional
problems
DMA.1
Functional problems table
Short description
Revision identifier
Detailed description
Single burst DMA memory-to-memory transfers have
additional memory cycles when the DMA source
memory is on the EMC bus.
When booting from NOR flash, SDRAM devices will not
release the data bus, preventing the LPC3240 from
booting correctly
Ethernet TxConsumeIndex register does not update
correctly after the first frame is sent
DDR EMC_D[15:0] to EMC_DQS[1:0] data output
set-up time, t
su(Q)
, for MCU write to DDR provides
limited timing margin
DDR interface has > 1.2 ns clock skew
An RTC match doesn't drive the ONSW pin active
(HIGH).
GPI_08 does not generate in interrupt signal.
Input pins (MCI0-2) on the Motor Control PWM
peripheral are not functional
High speed UART receive FIFO and status can freeze
USB host controller hangs on a dribble bit
‘-’, ‘A’
Section 3.1 on page 5
NOR.1
‘-’, ‘A’
Section 3.2 on page 7
Ethernet.1
‘-’, ‘A’
Section 3.3 on page 8
DDR.2
‘-’, ‘A’
Section 3.4 on page 8
DDR.1
RTC.1
‘-’, ‘A’
‘-’, ‘A’
Section 3.5 on page 11
Section 3.6 on page 12
INT.1
MCPWM.1
‘-’
‘-’, ‘A’
Section 3.7 on page 12
Section 3.8 on page 13
HSUART.1
USB.1
‘-’, ‘A’
‘-’, ‘A’
Section 3.9 on page 14
Section 3.10 on page 15
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC3240FET296,551 | 功能描述:ARM微控制器 - MCU ARM9 256KRAM VFP USB OTG ETH RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC3240FET296/01 | 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 266MHZ, TFBGA-296 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 266MHZ, TFBGA-296, Controller Family/Series:LPC3200, Core Size 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 266MHZ, TFBGA-296, Controller Family/Series:LPC3200, Core Size:16bit / 32bit, No. of I/O's:87, Supply Voltage Min:2.7V, Supply Voltage Max:3.6V, Digital IC Case Style:TFBGA, No. of Pins:296, Program Memory Size:-, |
| LPC3240FET296/01,5 | 功能描述:ARM微控制器 - MCU ARM9 VFP USB OTG Improved LCD RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC3240FET296/01,551 | 制造商:NXP Semiconductors 功能描述:0 |
| LPC3240FET296/015 | 制造商:NXP Semiconductors 功能描述:LPC3240FET296/TFBGA296/TRAYBDP |
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