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參數(shù)資料
| 型號(hào)： | LPC3240FET296 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARM926EJ-S with 256 kB SRAM, USB High-speed OTG, SD-MMC, NAND flash controller, Ethernet |
| 中文描述： | 32-BIT, FLASH, 266 MHz, RISC MICROCONTROLLER, PBGA296 |
| 封裝： | 15 X 15 MM, 0.70 MM PITCH, PLASTIC, MO-216, SOT1048-1, TFBGA-296 |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 121K |
| 代理商： | LPC3240FET296 |
ES_LPC3240
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 9 — 1 June 2011
11 of 17
NXP Semiconductors
ES_LPC3240
Errata sheet LPC3240
3.5 DDR.1: DDR interface has >1.2 ns clock skew
Introduction:
DDR memory uses a differential clock which is generated by the LPC3240. The
differential clock consists of two clock signals: EMC_CLK is the positive clock and
DDR_nCLK is the negative clock.
Problem:
There is approximately 1.27 ns of skew between the low transition of the DDR_nCLK and
the high transition of the EMC_CLK. This can cause two problems: 1) Some DDR devices
use this clock transition to drive a digital lock loop (DLL) in the DDR device. The DDR
clock skew can cause the DDR device's internal DLL to loose lock, resulting in the wrong
data being latched. 2) The DDR clock skew can also cause a reduced Data Valid Window
(also called Data-Out Window) from a DDR device. However, the LPC3240 has a
programmable DQS delay to achieve center alignment for accurate data reads.
Work-around:
Connecting the DDR device negative clock input (DDR_nCLK from the LPC3240) to the
DDR Reference Voltage (Vref - the midpoint of the DDR signal voltage swing, which is
generally VDDQ/2) avoids the clock skew problem, though it also eliminates the
advantages of differential signaling. The LPC3240 DDR_nCLK output should be left
unconnected. DDR Reference Voltage can be generated with a divide-by-two voltage
divider. Standard DDR memories usually require a Vref input, so this DDR reference
voltage should already be available. Mobile DDR devices typically do not have a Vref
input, so the external voltage divider may need to be added to the design for this
work-around.
It is also possible to compensate for the 1.27 ns clock skew by adding an additional
7 inches of pcb trace length to the EMC_CLK signal. However, this could have
unintentional consequences; such as increased Electro-Magnetic Interference.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC3240FET296,551 | 功能描述:ARM微控制器 - MCU ARM9 256KRAM VFP USB OTG ETH RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC3240FET296/01 | 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 266MHZ, TFBGA-296 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 266MHZ, TFBGA-296, Controller Family/Series:LPC3200, Core Size 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 266MHZ, TFBGA-296, Controller Family/Series:LPC3200, Core Size:16bit / 32bit, No. of I/O's:87, Supply Voltage Min:2.7V, Supply Voltage Max:3.6V, Digital IC Case Style:TFBGA, No. of Pins:296, Program Memory Size:-, |
| LPC3240FET296/01,5 | 功能描述:ARM微控制器 - MCU ARM9 VFP USB OTG Improved LCD RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC3240FET296/01,551 | 制造商:NXP Semiconductors 功能描述:0 |
| LPC3240FET296/015 | 制造商:NXP Semiconductors 功能描述:LPC3240FET296/TFBGA296/TRAYBDP |
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