ES_LPC3240
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NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 9 — 1 June 2011
11 of 17
NXP Semiconductors
ES_LPC3240
Errata sheet LPC3240
3.5 DDR.1: DDR interface has >1.2 ns clock skew
Introduction:
DDR memory uses a differential clock which is generated by the LPC3240. The
differential clock consists of two clock signals: EMC_CLK is the positive clock and
DDR_nCLK is the negative clock.
Problem:
There is approximately 1.27 ns of skew between the low transition of the DDR_nCLK and
the high transition of the EMC_CLK. This can cause two problems: 1) Some DDR devices
use this clock transition to drive a digital lock loop (DLL) in the DDR device. The DDR
clock skew can cause the DDR device's internal DLL to loose lock, resulting in the wrong
data being latched. 2) The DDR clock skew can also cause a reduced Data Valid Window
(also called Data-Out Window) from a DDR device. However, the LPC3240 has a
programmable DQS delay to achieve center alignment for accurate data reads.
Work-around:
Connecting the DDR device negative clock input (DDR_nCLK from the LPC3240) to the
DDR Reference Voltage (Vref - the midpoint of the DDR signal voltage swing, which is
generally VDDQ/2) avoids the clock skew problem, though it also eliminates the
advantages of differential signaling. The LPC3240 DDR_nCLK output should be left
unconnected. DDR Reference Voltage can be generated with a divide-by-two voltage
divider. Standard DDR memories usually require a Vref input, so this DDR reference
voltage should already be available. Mobile DDR devices typically do not have a Vref
input, so the external voltage divider may need to be added to the design for this
work-around.
It is also possible to compensate for the 1.27 ns clock skew by adding an additional
7 inches of pcb trace length to the EMC_CLK signal. However, this could have
unintentional consequences; such as increased Electro-Magnetic Interference.
