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參數(shù)資料
| 型號(hào)： | LPC3240FET296 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARM926EJ-S with 256 kB SRAM, USB High-speed OTG, SD-MMC, NAND flash controller, Ethernet |
| 中文描述： | 32-BIT, FLASH, 266 MHz, RISC MICROCONTROLLER, PBGA296 |
| 封裝： | 15 X 15 MM, 0.70 MM PITCH, PLASTIC, MO-216, SOT1048-1, TFBGA-296 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 121K |
| 代理商： | LPC3240FET296 |
ES_LPC3240
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Errata sheet
Rev. 9 — 1 June 2011
8 of 17
NXP Semiconductors
ES_LPC3240
Errata sheet LPC3240
3.3 Ethernet.1: Ethernet TxConsumeIndex register does not update
correctly after the first frame is sent
Introduction:
The transmit consume index register defines the descriptor that is going to be transmitted
next by the hardware transmit process. After a frame has been transmitted hardware
increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has
been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is
empty and the transmit channel will stop transmitting until software produces new
descriptors.
Problem:
The TxConsumeIndex register is not updated correctly (from 0 to 1) after the first frame is
sent. After the next frame sent, the TxConsumeIndex register is updated by two (from 0 to
2). This only happens the very first time, so subsequent updates are correct (even those
from 0 to 1, after wrapping the value to 0 once the value of TxDescriptorNumber has been
reached)
Work-around:
Software can correct this situation in many ways; for example, sending a dummy frame
after initialization.
3.4 DDR.2: DDR EMC_D[15:0] to EMC_DQS[1:0] data output set-up time,
t
su(Q)
, for MCU write to DDR provides limited timing margin
Remark:
This affects both 1.8 V mobile and 2.5 V DDR SDRAM system implementations.
Introduction:
DDR memory interface signal EMC_DQS[1:0] is source synchronous, defined to be driven
by the MCU center aligned to the data EMC_D[15:0] for writes, while driven by the DDR
memory edge aligned to the EMC_D[15:0] for reads. The basic DDR write timing is shown
in the data sheet Fig 1.
Fig 3.
128 MB DDR SDRAM example
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC3240FET296,551 | 功能描述:ARM微控制器 - MCU ARM9 256KRAM VFP USB OTG ETH RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC3240FET296/01 | 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 266MHZ, TFBGA-296 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 266MHZ, TFBGA-296, Controller Family/Series:LPC3200, Core Size 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 266MHZ, TFBGA-296, Controller Family/Series:LPC3200, Core Size:16bit / 32bit, No. of I/O's:87, Supply Voltage Min:2.7V, Supply Voltage Max:3.6V, Digital IC Case Style:TFBGA, No. of Pins:296, Program Memory Size:-, |
| LPC3240FET296/01,5 | 功能描述:ARM微控制器 - MCU ARM9 VFP USB OTG Improved LCD RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC3240FET296/01,551 | 制造商:NXP Semiconductors 功能描述:0 |
| LPC3240FET296/015 | 制造商:NXP Semiconductors 功能描述:LPC3240FET296/TFBGA296/TRAYBDP |
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