NXP Semiconductors
ES_LPC3240
Errata sheet LPC3240
NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 June 2011
Document identifier: ES_LPC3240
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
6. Contents
1
2
3
3.1
Product identification . . . . . . . . . . . . . . . . . . . . 3
Errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional problems detail. . . . . . . . . . . . . . . . 5
DMA.1: Single burst DMA memory-to-memory
transfers have additional memory cycles when the
DMA source memory is on the EMC bus . . . . . 5
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7
NOR.1: When booting from NOR flash, SDRAM
devices will not release the data bus, preventing
the LPC3240 from booting correctly. . . . . . . . . 7
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Ethernet.1: Ethernet TxConsumeIndex register
does not update correctly after the first frame is
sent. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .8
DDR.2: DDR EMC_D[15:0] to EMC_DQS[1:0]
data output set-up time, t
su(Q)
, for MCU write to
DDR provides limited timing margin . . . . . . . . . 8
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .9
DDR.1: DDR interface has >1.2 ns clock skew 11
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .11
RTC.1: An RTC match doesn’t drive the ONSW
pin active (HIGH) . . . . . . . . . . . . . . . . . . . . . . 12
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .12
INT.1: GPI_08 does not generate an interrupt
signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .12
MCPWM.1: Input pins (MCI0-2) on the Motor
Control PWM peripheral are not functional. . . 13
Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . .13
HSUART.1: High speed UART receive FIFO and
status can freeze . . . . . . . . . . . . . . . . . . . . . . 14
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Introduction:. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 14
USB.1: USB host controller hangs on a dribble
bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Introduction:. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AC/DC deviations detail . . . . . . . . . . . . . . . . . 15
ESD.1: Weak ESD protection on Reset_N pad 15
Introduction:. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Problem:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10
4
4.1
5
5.1
5.2
5.3
6