參數(shù)資料
型號: LPC3220FET296
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM926EJ-S with 128 kB SRAM, USB High-speed OTG, SD-MMC, NAND flash controller
中文描述: 32-BIT, FLASH, 266 MHz, RISC MICROCONTROLLER, PBGA296
封裝: 15 X 15 MM, 0.70 MM PITCH, PLASTIC, MO-216, SOT1048-1, TFBGA-296
文件頁數(shù): 61/79頁
文件大?。?/td> 599K
代理商: LPC3220FET296
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
61 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
11.4 DDR SDRAM controller
[1]
All values valid for EMC pads set to fast slew rate at 1.8 V unless otherwise specified (see SDRAMCLK_CTRL register in the
LPC32x0
User manual
).
[2]
CMD_DLY = COMMAND_DELAY bitfield in SDRAMCLK_CTRL[18:14] register, see
External Memory Controller (EMC) chapter in
LPC32x0 User manual
.
[3]
Applies to signals EMC_DQM[3:0], EMC_DYCS[1:0], EMC_RAS, EMC_CAS, EMC_WR, EMC_CKE[1:0].
[4]
DQS_DELAY, see
LPC32x0 User manual, External Memory Controller Chapter, Section 8 DDR DQS delay calibration
for details on
configuring this value.
[5]
Test conditions for measurements: T
amb
=
40
C to +85
C; operating frequency range f
oper
= 52 MHz to 133 MHz; EMC_DQM[3:0] and
EMC_D[31:0] driving 2 inches of 50
characteristic impedance trace with 10 pF capacitive load; no external source series termination
resistors used. EMC pads set to fast slew rate at 1.8 V or 2.5 V (see SDRAMCLK_CTRL register in the
LPC32x0 User manual
).
Table 14.
C
L
= 25 pF, T
amb
= 25
C, unless otherwise specified.
Symbol
Parameter
f
oper
operating frequency
t
CK
clock cycle time
t
CL
CK LOW-level width
t
CH
CK HIGH-level width
t
d(V)ctrl
control valid delay time
t
h(ctrl)
control hold time
t
d(AV)
address valid delay time
t
h(A)
address hold time
t
su(Q)
data output set-up time
EMC DDR SDRAM memory interface dynamic characteristics
[1]
Conditions
Min
-
7.5
-
-
Typical
104
9.6
0.5
t
CK
0.5
t
CK
(CMD_DLY
0.25) + 1.5
(CMD_DLY
0.25)
1.5
(CMD_DLY
0.25) + 1.5
(CMD_DLY
0.25)
1.5
0.15
t
CK
Max
133
-
-
-
-
-
-
-
0.25
t
CK
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
[2][3]
-
[2][3]
-
[2]
-
-
0.08
t
CK
[2]
EMC_D[31:0]
and
EMC_DQM[3:0]
to
EMC_DQS[1:0]
out
EMC_D[31:0]
and
EMC_DQM[3:0]
to
EMC_DQS[1:0]
out
for WRITE
command
for WRITE
command
for DQS out
[5]
t
h(Q)
data output hold time
[5]
0.25
t
CK
0.35
t
CK
0.42
t
CK
ns
t
DQSH
DQS HIGH time
-
0.5
t
CK
-
ns
t
DQSL
DQS LOW time
-
0.5
t
CK
-
ns
t
DQSS
WRITE command to first DQS latching
transition time
DQS falling edge to CK set-up time
DQS falling edge hold time from CK
DQS delay time
data input set-up time
data input hold time
-
t
CK
+ 0.7
-
ns
t
DSS
t
DSH
t
d(DQS)
t
su(D)
t
h(D)
for DQS in
for DQS in
for DQS in
-
-
-
-
-
0.5
t
CK
0.5
t
CK
DQS_DELAY
0.3
0.5
-
-
-
-
-
ns
ns
ns
ns
ns
[4]
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