- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385498 > LPC3220FET296 (NXP SEMICONDUCTORS) ARM926EJ-S with 128 kB SRAM, USB High-speed OTG, SD-MMC, NAND flash controller PDF資料下載
參數(shù)資料
| 型號： | LPC3220FET296 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARM926EJ-S with 128 kB SRAM, USB High-speed OTG, SD-MMC, NAND flash controller |
| 中文描述： | 32-BIT, FLASH, 266 MHz, RISC MICROCONTROLLER, PBGA296 |
| 封裝： | 15 X 15 MM, 0.70 MM PITCH, PLASTIC, MO-216, SOT1048-1, TFBGA-296 |
| 文件頁數(shù)： | 39/79頁 |
| 文件大?。?/td> | 599K |
| 代理商： | LPC3220FET296 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
39 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
There is a separate slave transmit FIFO. The slave transmit FIFO (TXS) and its level are
only available when the controller is configured as a Master/Slave device and is operating
in a multi-master environment. Separate TX FIFOs are needed in a multi-master because
a controller might have a message queued for transmission when an external master
addresses it to be come a slave-transmitter, a second source of data is needed.
Note that the I
2
C clock must be enabled in the I2CCLK_CTRL register before using the
I
2
C. The I
2
C clock can be disabled between communications, if used as a single master
I
2
C-bus interface, software has full control of when I
2
C communication is taking place on
the bus.
7.8.4.1
Features
The two I
2
C-bus blocks are standard I
2
C-bus compliant interfaces that may be used in
Single-master, Multi-master or Slave modes.
Programmable clock to allow adjustment of I
2
C-bus transfer rates.
Bidirectional data transfer.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
7.8.5
I
2
S-bus audio controller
The I
2
S-bus provides a standard communication interface for digital audio applications
The I
2
S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. Each I
2
S connection can act as a master or a slave. The
master connection determines the frequency of the clock line and all other slaves are
driven by this clock source. The two I
2
S-bus interfaces on the LPC3220/30/40/50 provides
a separate transmit and receive channel, providing a total of two transmit channels and
two receive channels. Each I
2
S channel supports monaural or stereo formatted data.
7.8.5.1
Features
The interface has separate input/output channels each of which can operate in master
or slave mode.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
Supports standard sampling frequencies (8 kHz, 11.025 kHz, 16 kHz, 22.05 kHz,
32 kHz, 44.1 kHz, 48 kHz, 96 kHz).
Word select period can be configured in master mode (separately for I
2
S input and
output).
Two eight-word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
Controls include reset, stop, and mute options separately for I
2
S input and I
2
S output.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LPC3230FET296 | ARM926EJ-S with 256 kB SRAM, USB High-speed OTG, SD-MMC, NAND flash controller, LCD controller |
| LPC3240FET296 | ARM926EJ-S with 256 kB SRAM, USB High-speed OTG, SD-MMC, NAND flash controller, Ethernet |
| LPV531 | Programmable Micropower CMOS Input, Rail-to-Rail Output Operational Amplifier |
| LPV531MK | Programmable Micropower CMOS Input, Rail-to-Rail Output Operational Amplifier |
| LPV531MKX | Programmable Micropower CMOS Input, Rail-to-Rail Output Operational Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC3220FET296,551 | 功能描述:ARM微控制器 - MCU ARM9 128KRAM VFP USB OTG RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LPC3220FET296/01,5 | 功能描述:ARM微控制器 - MCU ARM9 VFP USB OTG Improved LCD RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LPC3220FET296/01,551 | 制造商:NXP Semiconductors 功能描述:0 |
| LPC3230 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface |
| LPC3230FET296 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。