參數(shù)資料
型號(hào): LPC3220FET296
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM926EJ-S with 128 kB SRAM, USB High-speed OTG, SD-MMC, NAND flash controller
中文描述: 32-BIT, FLASH, 266 MHz, RISC MICROCONTROLLER, PBGA296
封裝: 15 X 15 MM, 0.70 MM PITCH, PLASTIC, MO-216, SOT1048-1, TFBGA-296
文件頁(yè)數(shù): 60/79頁(yè)
文件大?。?/td> 599K
代理商: LPC3220FET296
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
60 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
11.3 SDR SDRAM Controller
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical values valid for EMC pads set to fast slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or slower slew rate: VDD_EMC = 3.3 V,
VDD_CORE = 1.2 V (see SDRAMCLK_CTRL register in the
LPC32x0 User manual
).
[3]
All min or max values valid for EMC pads set to fast slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or slower slew rate: VDD_EMC
= 3.3 V, VDD_CORE = 1.2 V.
[4]
f
oper
= 1/t
CK.
Applies to signals: EMC_DQM[3:0], EMC_DYCS[1:0], EMC_RAS, EMC_CAS, EMC_WR, EMC_CKE[1:0].
[5]
[6]
CMD_DLY = COMMAND_DELAY bitfield in SDRAMCLK_CTRL[18:14] register, see
External Memory Controller (EMC) chapter in
LPC32x0 User manual
.
Table 13.
C
L
= 25 pF, T
amb
=
40
C to +85
C, unless otherwise specified.
[1][3]
Symbol
Parameter
f
oper
operating frequency
t
CK
clock cycle time
t
CL
CK LOW-level width
t
CH
CK HIGH-level width
t
d(V)ctrl
control valid delay time
t
h(ctrl)
control hold time
t
d(AV)
address valid delay time
t
h(A)
address hold time
t
d(QV)
data output valid delay time
t
h(Q)
data output hold time
t
su(D)
data input set-up time
t
h(D)
data input hold time
t
QZ
data output high-impedance time
EMC SDR SDRAM memory interface dynamic characteristics
Min
Typical
[2]
104
9.6
4.8
4.8
(CMD_DLY
0.25) + 2.7
(CMD_DLY
0.25) + 1.2
(CMD_DLY
0.25) + 3.2
(CMD_DLY
0.25) + 1.2
(CMD_DLY
0.25) + 3.5
(CMD_DLY
0.25) + 1.2
0.6
0.9
-
Max
133
-
-
-
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[4]
7.5
-
-
[5][6]
-
[5][6]
-
[6]
-
[6]
-
[6]
-
[6]
-
-
-
t
CK
-
-
-
Fig 9.
SDR SDRAM signal timing
002aae420
EMC_CLK
output signal (O)
input signal (I)
t
d(V)ctrl
, t
d(AV)
, t
d(QV)
t
h(ctrl)
,
t
h(Q)
, t
h(A)
t
h(D)
t
su(D)
t
CK
t
CL
t
CH
t
QZ
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