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參數(shù)資料
| 型號： | LPC3220FET296 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | ARM926EJ-S with 128 kB SRAM, USB High-speed OTG, SD-MMC, NAND flash controller |
| 中文描述： | 32-BIT, FLASH, 266 MHz, RISC MICROCONTROLLER, PBGA296 |
| 封裝： | 15 X 15 MM, 0.70 MM PITCH, PLASTIC, MO-216, SOT1048-1, TFBGA-296 |
| 文件頁數(shù)： | 31/79頁 |
| 文件大小： | 599K |
| 代理商： | LPC3220FET296 |
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LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
31 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
packet filtering and wake-up on LAN activity. Automatic frame transmission and reception
with scatter-gather DMA off-loads many operations from the CPU. The Ethernet DMA can
access off-chip memory via the EMC, as well as the IRAM. The Ethernet block interfaces
between an off-chip Ethernet PHY using the Media Independent Interface (MII) or
Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management
(MIIM) serial bus.
7.6.2.1
Features
Ethernet standards support:
–
Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
–
Fully compliant with IEEE standard 802.3.
–
Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
pressure.
–
Flexible transmit and receive frame options.
–
Virtual Local Area Network (VLAN) frame support.
Memory management:
–
Independent transmit and receive buffers memory mapped to SRAM.
–
DMA managers with scatter/gather DMA and arrays of frame descriptors.
–
Memory traffic optimized by buffering and pre-fetching.
Enhanced Ethernet features:
–
Receive filtering.
–
Multicast and broadcast frame support for both transmit and receive.
–
Optional automatic Frame Check Sequence (FCS) insertion with Circular
Redundancy Check (CRC) for transmit.
–
Selectable automatic transmit frame padding.
–
Over-length frame support for both transmit and receive allows any length frames.
–
Promiscuous receive mode.
–
Automatic collision back-off and frame retransmission.
–
Includes power management by clock switching. Wake-on-LAN power
management support allows system wake-up using the receive filters or a magic
frame detection filter.
Physical interface
–
Attachment of external PHY chip through standard MII or RMII interface.
–
PHY register access is available via the MIIM interface.
7.6.3
USB interface
The LPC3220/30/40/50 supports USB in either device, host, or OTG configuration.
7.6.3.1
USB device controller
The USB device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of register interface, serial interface engine, endpoint buffer memory and DMA
controller. The serial interface engine decodes the USB data stream and writes data to the
appropriate end point buffer memory. The status of a completed USB transfer or error
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LPC3220FET296,551 | 功能描述:ARM微控制器 - MCU ARM9 128KRAM VFP USB OTG RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LPC3220FET296/01,5 | 功能描述:ARM微控制器 - MCU ARM9 VFP USB OTG Improved LCD RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LPC3220FET296/01,551 | 制造商:NXP Semiconductors 功能描述:0 |
| LPC3230 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface |
| LPC3230FET296 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface |
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