參數(shù)資料
型號: LPC3220FET296
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM926EJ-S with 128 kB SRAM, USB High-speed OTG, SD-MMC, NAND flash controller
中文描述: 32-BIT, FLASH, 266 MHz, RISC MICROCONTROLLER, PBGA296
封裝: 15 X 15 MM, 0.70 MM PITCH, PLASTIC, MO-216, SOT1048-1, TFBGA-296
文件頁數(shù): 53/79頁
文件大?。?/td> 599K
代理商: LPC3220FET296
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 20 October 2011
53 of 79
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
10.1 Minimum core voltage requirements
Figure 4
shows the minimum core supply voltage that should be applied for a given core
frequency on pin VDD_CORE to ensure stable operation of the LPC3220/30/40/50.
10.2 Power supply sequencing
The LPC32x0 has no power sequencing requirements, that is, V
DD(1V2)
, V
DD(EMC)
, V
DD(IO)
,
and V
DDA(3V3)
can be switched on or off independent of each other. An internal circuit
ensures that the system correctly powers up in the absence of core power. During IO
power-up this circuit takes care that the system is powered in a defined mode. The same
is valid for core power-down.
10.3 Power consumption per peripheral
Table 9.
T
amb
= 25
C;
CPU clock = 208 MHz; I-cache/D-cache, MMU disabled; VDD_CORE = 1.2 V;
V
DD(IO)
= 1.8 V; USB AHB, IRAM, and IROM clocks always on; all peripherals are at their default
state at reset. Peripheral clocks are disabled except for peripheral measured.
Peripheral
High-speed UART (set to 115 200 Bd (8N1))
I
2
C-bus
SSP
I
2
S
DMA
EMC
Multi-level NAND controller
Single-level NAND controller
LCD
Ethernet MAC
[1]
[1]
All three Ethernet clocks are in enabled in the MAC_CLK_CTRL register (see
LPC32x0 User manual
).
Fig 4.
Minimum required core supply voltage for different core frequencies
core frequency (MHz)
160
280
240
200
002aae872
1.0
1.2
1.4
0.8
VDD_CORE
(V)
Power consumption per peripheral
I
DD(run)
/ mA
0.3
0.3
0.6
0.5
6.3
7.3
1.4
0.3
5.6
2.9
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