參數(shù)資料
型號: LMX2353TMX/NOPB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: PLL合成/DDS/VCOs
英文描述: PHASE LOCKED LOOP, 2500 MHz, PDSO16
封裝: LEAD FREE, PLASTIC, TSSOP-16
文件頁數(shù): 6/16頁
文件大?。?/td> 209K
代理商: LMX2353TMX/NOPB
2.0 Programming Description (Continued)
The low gain or steadystate mode for fastlocking is defined to be whenever the charge pump current selected is less than 900
A. The high gain or acquisition mode is defined to be whenever the charge pump current is greater or equal to 900 A. (The logic
setting of the CP_8X bit determines which of the two gain modes the user is in.) During the acquisition phase when the CP_8X
bit is set to a HIGH state, the OUT0 output becomes active LOW thereby altering the loop’s damping resistance.
The acquisition phase is terminated by setting the CP_8X bit LOW resulting in the OUT0 output being OFF or TRI-STATE. When
in fastlock mode, the OUT_0 and OUT_1 bits are don’t care bits, and the OUT1 output is at TRI-STATE.
TEST MODE: The OUT0/OUT1 test mode occurs when the TEST bit (F2_17) is set HIGH. This mode is intended for NSC pro-
duction test only. Selecting this mode overrides the FASTLOCK and GEN PURPOSE modes.
2.5.4 Serial Data Input Timing
DS101124-8
Notes: Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around Vcc/2. The test waveform has an edge rate of 0.6 V/ns with
amplitudes of 2.2V @ VCC = 2.7V and 2.6V VCC = 5.5V.
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參數(shù)描述
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