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參數資料
| 型號： | LMX2353TMX/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 2500 MHz, PDSO16 |
| 封裝： | LEAD FREE, PLASTIC, TSSOP-16 |
| 文件頁數： | 3/16頁 |
| 文件大小： | 209K |
| 代理商： | LMX2353TMX/NOPB |
2.0 Programming Description (Continued)
R:
Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P:
Preset modulus of dual modulus prescaler (P = 16 or 32)
2.4 F1 REGISTER
If the ADDRESS[1:0] field is set to 0 0, data is transferred from the 24-bit shift register into the F1 register when Latch Enable (LE)
signal goes high . The F1 register sets the fractional divider denominator FRAC_16 bit and F
out/ Lock Dectect output FoLD word.
The rest of the bits F1_0 - F1_16, and F1_21 are Don’t Care.
Most Significant Bit
SHIFT REGISTER BIT LOCATION
Least Significant Bit
23
22
21
20
19
18
17
16
15
14
13
12
11
10
987654
3
2
1
0
Data Field
Address Field
X
FRAC
_16
F
oLD
DON’T CARE
00
F1
_21
F1
_20
F1
_19
F1
_18
F1
_17
F1
_16
F1
_15
F1
_14
F1
_13
F1
_12
F1
_11
F1
_10
F1
_9
F1
_8
F1
_7
F1
_6
F1
_5
F1
_4
F1
_3
F1
_2
F1
_1
F1
_0
2.4.1 FRAC_16
The FRAC_16 bit is used to set the fractional compensation at either 1/16 or 1/15 resolution. When FRAC_16 bit is set to one,
the fractional modulus is set to 1/16 resolution, and FRAC_16 = 0 corresponds to 1/15. See section 2.3.5 for fractional divider
values.
Bit
Location
Function
0
1
FRAC_16
F1_20
Fractional Modulus
1/15
1/16
2.4.2 F
oLD
The F
oLD word is used to set the function of the Lock Detect output pin according to the Table 2.4.2.1 below. Open drain lock de-
tect output is provided to indicate when the VCO frequency is in “l(fā)ock”. When the loop is locked and a lock detect mode is se-
lected, the pin is HIGH, with narrow pulses LOW. See typical Lock detect timing in section 2.4.2.4.
2.4.2.1 F
OLD Programming Truth Table
F1_19
F1_18
F1_17
F
oLD Output State
0
Analog Lock Detect
(Open Drain)
0
1
Reserved
0
1
0
Digital Lock Detect
0
1
Reserved
1
0
Reserved
1
0
1
Reserved
1
0
N Divider Output
1
R Divider Output
Reserved - Denotes a disallowed programming condition.
2.4.2.2 Lock Detect (LD) Digital Filter
The LD Digital Filter compares the difference between the phase of the inputs of the phase detector to a RC generated delay of
approximately 15 ns. To enter the locked state (Lock = HIGH) the phase error must be less than the 15 ns RC delay for 5 con-
secutive reference cycles. Once in lock (Lock = HIGH), the RC delay is changed to approximately 30 ns. To exit the locked state
(Lock = LOW), the phase error must become greater than the 30 ns RC delay. If the PLL is unlocked, the lock detect output will
be forced LOW. A flow chart of the digital filter is shown next.
www.national.com
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