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參數(shù)資料
| 型號： | LMX2353TMX/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 2500 MHz, PDSO16 |
| 封裝： | LEAD FREE, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 209K |
| 代理商： | LMX2353TMX/NOPB |
2.0 Programming Description (Continued)
2.2.4.2 Phase Detector Polarity
(PD_POL)
Depending upon VCO characteristics, the PD_POL (R_15) bit should be set accordingly:
When VCO characteristics are positive like (1), PD_POL should be set HIGH;
When VCO characteristics are negative like (2), PD_POL should be set LOW.
2.3 N REGISTER
If the ADDRESS[1:0] field is set to 1 1, data is transferred from the 24-bit shift register into the N register which sets the PLL’ s
19-bit N-counter, prescaler value, counter reset, and power-down bit. The 19-bit N counter consists of a 4-bit fractional numerator,
FRAC_CNTR[3:0], a 5-bit swallow counter, A_CNTR[4:0], and a 10-bit programmable counter, B_CNTR[9:0]. Serial data format
is show below. The divide ratio (NB_CNTR) must be
≥ 3, and must be ≥ swallow counter +2; NB_CNTR ≥ (NA_CNTR +2).
Most Significant Bit
SHIFT REGISTER BIT LOCATION
Least Significant Bit
23
22
21
20
19
18
17
16
15
14
13
12
11 10
9876
5
4
3
2
1
0
Data Field
Address Field
CTL_WORD[2:0]
NB_CNTR[9:0]
NA_CNTR[4:0]
FRAC_CNTR[3:0]
11
N
_21
N
_20
N
_19
N
_18
N
_17
N
_16
N
_15
N
_14
N
_13
N
_12
N
_11
N
_10
N
_9
N
_8
N
_7
N
_6
N
_5
N
_4
N
_3
N
_2
N
_1
N
_0
2.3.1 CTL_WORD
(N_19 -N_21)
N_21
N_20
N_19
CNT_RST
PWDN
PRESC_SEL
2.3.2 Control Word Truth Table
Bit
Location
Function
0
1
PRESC_SEL
N_19
Prescaler Modulus Select
16/17
(0.5 GHz to 1.2 GHz)
32/33
(1.2 GHz to 2.5 GHz)
PWDN
N_20
Power Down
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CNT_RST
N_21
Counter Reset
Normal
Operation
Reset
PWDN_MODE
F2_19
Power Down Mode Select
Asynchronous
Power Down
Synchronous
Power Down
2.3.2.1 Counter Reset
(CNT_RST)
The Counter Reset enable bit when activated allows the reset of both N and R counters. Upon removal of the reset bit, the N
counter resumes counting in “close” alignment with the R counter (the maximum error is one prescaler cycle).
2.3.2.2 Power Down
(PWDN)
Activation of the PLL PWDN bit results in the disabling of the N counter divider and de-biasing of the f
IN input (to a high impedance
state). The R counter functionality also becomes disabled when the power down bit is activated. The OSCin pin reverts to a high
impedance state as well during power down. Power down forces the charge pump and phase comparator logic to a TRI-STATE
condition. The MICROWIRE control register remains active and capable of loading and latching in data during all of the power
down modes.
2.3.2.3 Prescaler Modulus Select
(PRESC_SEL)
The PRESC_SEL bit is used to set the RF prescaler modulus value. The LMX2353 is capable of operating from 500 MHz to
1.2 GHz with the 16/17 prescaler, and 1.2 GHz to 2.5 GHz with the 32/33 prescaler selection.
VCO CHARACTERISTICS
DS101124-4
www.national.com
9
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