- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄44574 > LMX2353TMX/NOPB (NATIONAL SEMICONDUCTOR CORP) PHASE LOCKED LOOP, 2500 MHz, PDSO16 PDF資料下載
參數(shù)資料
| 型號： | LMX2353TMX/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 2500 MHz, PDSO16 |
| 封裝： | LEAD FREE, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 209K |
| 代理商： | LMX2353TMX/NOPB |
2.0 Programming Description (Continued)
2.3.2.4 Power Down Mode
(PWDN_MODE)
Synchronous Power Down Mode
The PLL loop can be synchronously powered down by setting the PWDN mode bit HIGH (F2_19=1) and then asserting the power
down mode bit (N20 = 1). The power down function is gated by the charge pump. Once the power down program bit is loaded,
the part will go into power down mode upon the completion of a charge pump pulse event.
Asynchronous Power Down Mode
The PLL loop can be asynchronously powered down by setting the PWDN mode bit LOW (F2_19=0) and then asserting the
power down mode bit (N20 = 1). The power down function is NOT gated by the charge pump. Once the power down program bit
is loaded, the part will go into power down mode immediately.
2.3.3 Feedback Divide Ratio
(NB Counter)
NB_CNTR[9:0]
Divide Ratio
N_18
N_17
N_16
N_15
N_14
N_13
N_12
N_11
N_10
N_9
3
000000001
1
4
000000010
0
1023
111111111
1
Note: B-counter divide ratio must be
≥ 3.
NB_CNTR
≥ (NA_CNTR +2).
2.3.4 Swallow Counter Divide Ratio
(NA Counter)
NB_CNTR[4:0]
Divide Ratio
N_8
N_7
N_6
N_5
N_4
0
00000
1
00001
31
11111
Note: Swallow Counter Value: 0 to 31.
NB_CNTR
≥ (NA_CNTR +2).
2.3.5 Fractional Modulus Accumulator
(FRAC_CNTR)
Divide
Ratio
Divide
Ratio
FRAC_CNTR[3:0]
Modulus 15
Modulus 16
N_3
N_2
N_1
N_0
0
0000
1/15
1/16
0001
2/15
2/16
0010
14/15
14/16
1110
N/A
15/16
1111
2.3.6 Pulse Swallow Function
f
VCO = [N+F] x [fOSC/R] where N = (PxB) + A
f
VCO:
Output frequency of external voltage controlled oscillator (VCO)
F:
Fractional ratio (contents of FRAC_CNTR divided by the fractional modulus)
B:
Preset divide ratio of binary 10-bit programmable counter (3 to 1023)
A:
Preset divide ratio of binary 5-bit swallow counter
0 < A < 31 {P=32};
0 < A < 15 {P=16};
A+2 < B
f
OSC:
Output frequency of the external reference frequency oscillator
www.national.com
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMX2354SLBX/NOPB | PLL FREQUENCY SYNTHESIZER, 2500 MHz, QCC24 |
| LMX2354TM/NOPB | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO24 |
| LMX2354SLDX | PLL FREQUENCY SYNTHESIZER, 2500 MHz, CQCC24 |
| LMX2355SLBX | PLL FREQUENCY SYNTHESIZER, 2500 MHz, QCC24 |
| LMX2370SLDX | PLL FREQUENCY SYNTHESIZER, 2500 MHz, QCC24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2354 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer |
| LMX2354SLB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer |
| LMX2354SLBX | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| LMX2354SLBX/NOPB | 功能描述:IC FREQ SYNTH DUAL 24-LAMCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2354SLDX | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。