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參數(shù)資料
| 型號： | LMX2353TMX/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 2500 MHz, PDSO16 |
| 封裝： | LEAD FREE, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 209K |
| 代理商： | LMX2353TMX/NOPB |
2.0 Programming Description (Continued)
2.4.2.4 Typical Lock Detecting Timing
2.5 F2 REGISTER
If the ADDRESS[1:0] field is set to 0 1, data is transferred from the 24-bit shift register into the F2 register when Latch Enable (LE)
signal goes high. The F2 register sets the CMOS output word bit CMOS[3:0] and the power down mode bit PWDN_MODE. The
rest of the bits F2_0 - F2_14, and F2_20-F_21 are Don’t Care.
Most Significant Bit
SHIFT REGISTER BIT LOCATION
Least Significant Bit
23
22
21
20
19
18
17
16
15
14
13
12
11 10
987654
3
2
1
0
Data Field
Address Field
DON’T
CARE
PWDN_
MODE
CMOS[3:0]
DON’T CARE
00
F2
_21
F2
_20
F2
_19
F2
_18
F2
_17
F2
_16
F2
_15
F2
_14
F2
_13
F2
_12
F2
_11
F2
_10
F2
_9
F2
_8
F2
_7
F2
_6
F2
_5
F2
_4
F2
_3
F2
_2
F2
_1
F2
_0
2.5.1 PWDN_MODE
(F2_19)
See section 2.3.2 describing the control word and power down.
2.5.2 Programmable CMOS Outputs
(F2_15–F2_18)
F2_18
F2_17
F2_16
F2_15
FastLock
TEST
OUT_1
OUT_0
2.5.3 OUT0/OUT1 Truth Table
Bit
Location
Function
0
1
OUT_0
F2_15
Set the output logic level of
OUT0 pin
LOW
HIGH
OUT_1
F2_16
Set the output logic level of
OUT1 pin
LOW
HIGH
TEST
F2_17
Test
Normal Operation
Test Mode
FastLock
F2_18
FastLock Mode
CMOS Output Mode
FastLock Mode
The CMOS[3:0] 4-bit register selects one of three modes for the OUT_0 and OUT_1 pins. The OUT_0 and OUT_1 pins are nor-
mally used as general purpose CMOS outputs or as part of a fastlock scheme. There is also a production test mode that overrides
the other two normal modes when activated.
GENERAL PURPOSE CMOS OUTPUT MODE: The general purpose CMOS output mode is selected when the Fastlock bit
(F2_F18) and TEST bit (F2_17) are set LOW. The logic levels of the OUT_0 bit (F2_15) and OUT_1 bit (F2_16) then determine
the logic states of the OUT_0 and OUT_1 pins.
FASTLOCK MODE: The Fastlock bit (F2_18) selects between the general purpose CMOS output or fastlock modes. The fastlock
mode is selected when the fastlock bit is HIGH. The fastlock mode allows the user to open up the loop bandwidth momentarily
while acquiring lock by increasing the charge pump output current magnitude while simultaneously switching in a second resistor
element to ground via the OUT0 output pin.
DS101124-7
www.national.com
13
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