參數(shù)資料
型號： LMK04002BISQE/NOPB
廠商： National Semiconductor
文件頁數(shù)： 5/65頁
文件大小： 0K
描述： IC CLOCK COND 1.6GHZ W/PLL 48LLP
標(biāo)準(zhǔn)包裝： 1
系列： PowerWise®
類型： 時(shí)鐘調(diào)節(jié)器
PLL： 是
輸入： LVCMOS
輸出： LVCMOS，2VPECL，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:7
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.75GHz
除法器/乘法器： 是/是
電源電壓： 3.15 V ~ 3.45 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-LLP（7x7）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1275 (CN2011-ZH PDF)
其它名稱： LMK04002BISQEDKR
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V
≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LMK040x0 (13)
BW = 12 kHz to 20 MHz
105
fVCO = 1200 MHz
BW = 100 Hz to 20 MHz
110
Integrated RMS Jitter
LMK040x1 (14)
BW = 12 kHz to 20 MHz
100
fVCO = 1500 MHz
BW = 100 Hz to 20 MHz
105
Integrated RMS Jitter
JFout
fs
LMK040x2 (15)
BW = 12 kHz to 20 MHz
95
fVCO = 1600 MHz
BW = 100 Hz to 20 MHz
100
Integrated RMS Jitter
LMK040x3 (16)
BW = 12 kHz to 20 MHz
105
fVCO = 2000 MHz
BW = 100 Hz to 20 MHz
110
Integrated RMS Jitter
CLKout's Internal VCO Closed Loop Phase Noise and Jitter Specifications using an Instrumentation Quality VCXO
Offset = 1 kHz
-125
LMK040x0 (17)
fCLKout = 250 MHz
Offset = 10 kHz
-130
SSB Phase Noise
Offset = 100 kHz
-132
Measured at Clock Outputs
Offset = 1 MHz
-148
Value is average for all output
types
Offset = 10 MHz
-157
Offset = 1 kHz
-126
LMK040x1 (18)
fCLKout = 250 MHz
Offset = 10 kHz
-133
SSB Phase Noise
Offset = 100 kHz
-136
Measured at Clock Outputs
Offset = 1 MHz
-147
Value is average for all output
types
Offset = 10 MHz
-156
L(f)CLKout
dBc/Hz
Offset = 1 kHz
-127
LMK040x2 (19)
fCLKout = 250 MHz
Offset = 10 kHz
-133
SSB Phase Noise
Offset = 100 kHz
-134
Measured at Clock Outputs
Offset = 1 MHz
-145
Value is average for all output
types
Offset = 10 MHz
-157
Offset = 1 kHz
-125
LMK040x3 (20)
fCLKout = 250 MHz
Offset = 10 kHz
-132
SSB Phase Noise
Offset = 100 kHz
-135
Measured at Clock Outputs
Offset = 1 MHz
-145
Value Is average for all output
types
Offset = 10 MHz
-156
(17) For LMK040x0, fVCO = 1250 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
251 kHz, PM = 76°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
CLKoutX_DIV = Bypass. CLKout_DLY = OFF.
(18) For LMK040x1, fVCO = 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
268 kHz, PM = 75°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
CLKoutX_DIV = 2. CLKout_DLY = OFF.
(19) For LMK040x2, fVCO = 1750 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
354 kHz, PM = 73°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
CLKoutX_DIV = Bypass. CLKout_DLY = OFF.
(20) For LMK040x3, fVCO = 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW
= 434 kHz, PM = 69°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
CLKoutX_DIV = 4. CLKout_DLY = OFF.
Copyright 2008–2011, Texas Instruments Incorporated
13
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