參數(shù)資料
型號(hào)： LMK04002BISQE/NOPB
廠(chǎng)商： National Semiconductor
文件頁(yè)數(shù)： 48/65頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK COND 1.6GHZ W/PLL 48LLP
標(biāo)準(zhǔn)包裝： 1
系列： PowerWise®
類(lèi)型： 時(shí)鐘調(diào)節(jié)器
PLL： 是
輸入： LVCMOS
輸出： LVCMOS，2VPECL，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:7
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.75GHz
除法器/乘法器： 是/是
電源電壓： 3.15 V ~ 3.45 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 48-LLP（7x7）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 1275 (CN2011-ZH PDF)
其它名稱(chēng)： LMK04002BISQEDKR
CLKoutX
CLKoutX*
LVPECL
Receiver
1
2
0:
100: Trace
(Differential)
1
2
0:
Vcc
LVPECL
Driver
8
2:
8
2:
CLKoutX
CLKoutX*
LVPECL
Receiver
5
0:
100: Trace
(Differential)
5
0:
Vcc - 2 V
LVPECL
Driver
CLKoutX
CLKoutX*
LVDS
Receiver
1
0
0:
100: Trace
(Differential)
LVDS
Driver
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
It is possible to drive a non-LVPECL or non-LVDS receiver with an LVDS or LVPECL driver as long as the above
guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best
termination and coupling method to be sure that the receiver is biased at its optimum DC voltage (common mode
voltage). For example, when driving the OSCin/OSCin* input of the LMK04000 family, OSCin/OSCin* should be
AC coupled because OSCin/OSCin* biases the signal to the proper DC level (See Figure 13) This is only slightly
different from the AC coupled cases described in Driving CLKin Pins with a Single-Ended Source because the
DC blocking capacitors are placed between the termination and the OSCin/OSCin* pins, but the concept remains
the same. The receiver (OSCin/OSCin*) sets the input to the optimum DC bias voltage (common mode voltage),
not the driver.
Termination for DC Coupled Differential Operation
For DC coupled operation of an LVDS driver, terminate with 100
Ω as close as possible to the LVDS receiver as
shown in Figure 18.
Figure 18. Differential LVDS Operation, DC Coupling, No Biasing of the Receiver
For DC coupled operation of an LVPECL driver, terminate with 50
Ω to VCC - 2 V as shown in Figure 19.
Alternatively terminate with a Thevenin equivalent circuit (120
Ω resistor connected to VCC and an 82 Ω resistor
connected to ground with the driver connected to the junction of the 120
Ω and 82 Ω resistors) as shown in
Figure 20 for VCC = 3.3 V.
Figure 19. Differential LVPECL Operation, DC Coupling
Figure 20. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent
52
Copyright 2008–2011, Texas Instruments Incorporated
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LMK04002BISQX 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04002BISQX/NOPB 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
LMK04010BISQ 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04010BISQ/NOPB 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
LMK04010BISQE 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs
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