參數(shù)資料
型號(hào)： LMK04002BISQE/NOPB
廠商： National Semiconductor
文件頁數(shù)： 38/65頁
文件大?。?/td> 0K
描述： IC CLOCK COND 1.6GHZ W/PLL 48LLP
標(biāo)準(zhǔn)包裝： 1
系列： PowerWise®
類型： 時(shí)鐘調(diào)節(jié)器
PLL： 是
輸入： LVCMOS
輸出： LVCMOS，2VPECL，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:7
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.75GHz
除法器/乘法器： 是/是
電源電壓： 3.15 V ~ 3.45 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-LLP（7x7）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1275 (CN2011-ZH PDF)
其它名稱： LMK04002BISQEDKR
C
Po
u
t1
LEuWire
CLKuWire
DATAuWire
GOE
LD
(optional)
To Host
C
L
Ko
u
t0
C
L
Ko
u
t0
*
C
L
Ko
u
t1
*
C
L
Ko
u
t1
C
L
Ko
u
t2
B
C
L
Ko
u
t2
A
C
L
Ko
u
t3
*
C
L
Ko
u
t3
C
L
Ko
u
t4
*
C
L
Ko
u
t4
To
System
SYNC*
C
L
Ki
n
0
C
L
Ki
n
0
*
Bias
Vcc
LDObyp1
LDObyp2
10 PF
0.1 PF
1 PF
0.1 PF
LMK040xx
100
VCXO
OSCin
OSCin*
100
0.1 uF
CLKin1*
CLKin1
0.1 PF
To
System
To Host
CPout2
100 pF
To
System
Fout
Reference Clock #1
(Primary)
Reference Clock #2
(Secondary)
PLL1 Loop Filter
PLL2 Loop Filter
Rterm
0.1 PF
120
120
To
System
To
System
51
0.1 PF
120
120
To
System
0.47 PF
D
L
D
_
BYP
3
p
F
3
p
F
3
p
F
0.1 PF
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
APPLICATION INFORMATION
System Level Diagram
The following diagram illustrates the typical interconnection of the LMK040xx in a clocking application.
Figure 13. Typical Application
Figure 13 shows an LMK04000 family device with external circuitry. The primary reference clock input is at
CLKin0/0*. A secondary reference clock is driving CLKin1/1*. Both clocks are depicted as AC coupled differential
drivers. The VCXO attached to the OSCin/OSCin* port is configured as an AC coupled single-ended driver. Any
of the input ports (CLKin0/0*, CLKin1/1*, or OSCin/OSCin*) may be configured as either differential or single-
ended. These options are discussed later in the data sheet.
The diagram shows an optional connection between the LD pin and GOE. With this arrangement, the LD pin can
be programmed to output a lock detect signal that is active HIGH (see Table 29 for optional LD pin outputs). If
lock is lost, the LD pin will transition to a LOW, pulling GOE low and causing all clock outputs to be disabled.
This scheme should be used only if disabling the clock outputs is desirable when lock is lost.
Copyright 2008–2011, Texas Instruments Incorporated
43
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