
3.0 Register Description
(Continued)
Bit 13 selects unsigned/signed sample data
0: unsigned
1: signed
Bit 12 is loop mode enable bit.
0: disable
1: enable
Bit 11–0 (VOL) is channel volume attenuation in format of
6.6. 000h stands for 0 dB attenuation, FFFh stands for mute.
3.4.9.31 F4h_A (EBUF1) (Bank A Only)
This register can be accessed in index mode or direct ac-
cess mode.
Address:
AudioBase + F4h (index mode) || Audio MEM
Base + 814h + 20h*CIR (direct access mode,
CIR: channel index) (CIR
<
32)
Size:
32 bits
Type:
Read/Write
Default:
XXXXXXXXh
Description:
Envelope Buffer 1
This register and next one provide envelope double buffer.
Bit 31–30 (AMS_H) is Amplitude Modulation Step High part.
Bits 29–28 (EMOD) define operation mode.
00: DEC mode (ramp from 0 dB to 64 dB)
In this mode, bits 7–0 of this register are used as ECNT
which stores current state of a 8-bit counter; bits 15–8 of this
register are used as EINIT which provides initial value of that
8-bit counter; bits 27–16 of this register are used as EAMT
which is the absolute ramping amount with range from 0 dB
to 63 and 63/64 dB. Every 48 kHz clock, ECNT decrease 1;
every time when ECNT=00h, it reload EINIT, EAMT de-
crease 1, and Ec decrease 1; every time when EAMT=00h,
envelope engine will toggle buffer flag in global register
CEBC.
01: INC mode ( ramp from 64 dB to 0 dB )
4.0 Functional Description
In this mode, the layout of this register is completely the
same as in DEC mode. Engine works in the same way ex-
cept that the ramp direction is from 64 dB to 0 dB.
10: Delay mode
In this mode, bits 27–26 are used to select sub-mode:
00: Delay_hold
01: Delay_start
10: Delay_stop
11: reserved
19–0 is used as EDLY which store the current state of a 20-
bit delay counter, bits 25–20 are of no use. Every 48 kHZ
clock, EDLY decrease 1. During all the time this buffer active,
Ec keep unchanged.
In Delay_hold sub-mode, when EDLY =00000h, engine will
toggle current buffer flag in global register CEBC.
In Delay_start sub-mode, when EDLY =00000h, engine will
reset DLY flag register.
In Delay_stop sub-mode, when EDLY =00000h, engine will
reset start/stop flag register.
11: Still mode
In this mode, Ec keep unchanged, buffer never toggle auto-
matically. Only when CEBC is written, buffer may toggle.
3.4.9.32 F8h_A (EBUF2) (Bank A Only)
This register can be accessed in index mode or direct ac-
cess mode.
Address:
AudioBase + F8h (index mode) || Audio MEM
Base + 818h + 20h*CIR (direct access mode,
CIR: channel index) (CIR
<
32)
Size:
32 bits
Type:
Read/Write
Default:
XXXXXXXXh
Description:
Envelope Buffer 2
EBUF2 is totally as the same as EBUF1 except that bits
31–30 are AMS_L (Amplitude Modulation Step Low part).
DS100910-1
FIGURE 2. LM4560 Block Diagram
www.national.com
31