參數(shù)資料
型號： LM4560
廠商： National Semiconductor Corporation
英文描述： Advanced PCI Audio Accelerator
中文描述： 先進的PCI音頻加速器
文件頁數(shù)： 13/54頁
文件大小： 380K
代理商： LM4560
3.0 Register Description
(Continued)
3.4.1.2 DMAR1 (Legacy DMA Playback Buffer Base
Register Port2)
Address:
DDMASlaveBase + 1h or AudioBase + 1h or
0000h / 0002h
Size:
8 bits
Type:
Read/Write
Default:
00h
Write: Legacy DMA Playback Buffer Base Address 15–8
Legacy DMA Playback Buffer Current Transfer Address
15–8
Read: Legacy DMA Playback Buffer Current Transfer Ad-
dress 15–8
The PCI bus interface circuit should response to I/O read to
0000h or 0002h on the PCI bus only when DMASnoopEn is
active.
3.4.1.3 DMAR2 (Legacy DMA Playback Buffer Base
Register Port3)
Address:
DDMASlaveBase + 2h or AudioBase + 2h or
0087h / 0083h
Size:
8 bits
Type:
Read/Write
Default:
00h
Write: Legacy DMA Playback Buffer Base Address 23–16
Legacy DMA Playback Buffer Current Transfer Address
23–16
Read: Legacy DMA Playback Buffer Current Transfer Ad-
dress 23–16
The PCI bus interface circuit should response to I/O read to
0087h or 0083h on the PCI bus only when DMASnoopEn is
active.
3.4.1.4 DMAR3 (Legacy DMA Playback Buffer Base
Register Port4)
Address:
DDMASlaveBase + 3h or AudioBase + 3h
Size:
8 bits
Type:
Read/Write
Default:
00h
Write: Legacy DMA Playback Buffer Base Address 31–24
Legacy DMA Playback Buffer Current Transfer Address
31–24
Read: Legacy DMA Playback Buffer Current Transfer Ad-
dress 31–24
This register is intended for system which has DDMAMaster.
Any time when legacy DMA is running, this register must be
reset to 0 by software driver.
3.4.1.5 DMAR4 (Legacy DMA Playback Byte Count
Register 1)
Address:
DDMASlaveBase + 4h or AudioBase + 4h or
0001h / 0003h
Size:
8 bits
Type:
Read/Write
Default:
00h
Write : Legacy DMA Playback Byte Base Count 7–0
Legacy DMA Playback Current Byte Count 7–0
Read: Legacy DMA Playback Current Byte Count 7–0
The PCI bus interface circuit should response to I/O read to
0003h or 0001h on the PCI bus only when DMASnoopEn is
active.
3.4.1.6 DMAR5 (Legacy DMA Playback Byte Count
Register 2)
Address:
DDMASlaveBase + 5h or AudioBase + 5h or
0001h / 0003h
Size:
8 bits
Type:
Read/Write
Default:
00h
Write: Legacy DMA Playback Byte Base Count 15–8
Legacy DMA Playback Current Byte Count 15–8
Read: Legacy DMA Playback Current Byte Count 15–8
The PCI bus interface circuit should response to I/O read to
0003h or 0001h on the PCI bus only when DMASnoopEn is
active.
3.4.1.7 DMAR6 (Legacy DMA Playback Byte Count
Register 3)
Address:
DDMASlaveBase + 6h or AudioBase + 6h
Size:
8 bits
Type:
Read/Write
Default:
00h
Write: Legacy DMA Playback Byte Base Count 23–16
Legacy DMA Playback Current Byte Count 23–16
Read: Legacy DMA Playback Current Byte Count 23–16
This register is intended for system which has DDMAMaster.
Any time when legacy DMAplayback is not running, this reg-
ister must be reset to 0 by software driver.
3.4.1.8 DMAR7 (Legacy DMA Playback Misc. Register)
Address:
DDMASlaveBase + 7h or AudioBase + 7h
Size:
8 bits
Type:
Read/Write
Default:
00h
3.4.1.9 DMAR8 (Legacy DMA Controller Command /
Status Register)
Address:
DDMASlaveBase + 8h or AudioBase + 8h or
0008h
Size:
8 bits
Type:
Read Only
Default:
00h
Read: status register for implemented legacy 8237-A DMA
channel.
Implementation of this register maintains the compatibility
with legacy 8237-A status register. However, when reading
this register, the return value should be different for I/O read
to (DDMASlaveBase + 8h), I/O read to (AudioBase +8h) and
I/O read to (0008h). I/O read to (DDMASlaveBase + 08h) is
normally initiated by DDMAMaster. I/O read to (AudioBase +
08h) is normally initiated by our debug program. The DDMA
Master will take the responsibility to combine the return
value of each DMA Slave Channel in the system and return
the final resultant byte to response to the PCI I/O read to
0008h initiated by Host/PCI Bridge. The PCI bus interface
circuit should response to I/O read to 0008h on the PCI bus
only when DMASnoopEn is active.
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