參數(shù)資料
型號： LM4560
廠商： National Semiconductor Corporation
英文描述： Advanced PCI Audio Accelerator
中文描述： 先進的PCI音頻加速器
文件頁數(shù)： 12/54頁
文件大小： 380K
代理商： LM4560
3.0 Register Description
(Continued)
3.1.1.15.6 Legacy DMA Snooping:
If CFG_REG45h[1] is ‘1’, Audio Processor will trap either of
Legacy DMA channel 0 or 1 by snooping legacy DMA regis-
ter 00h–0Fh write cycle and response to read cycle.
Physically, these 16 byte registers are identical to Audio
Base Reg00h–0fh.
3.1.1.15.7 DDMA Base:
Audio Processor is also a DDMA slave which has a DDMA
base in CFG_REG40h and has 16 byte registers. Physically,
these 16 byte registers are identical to Audio Base
Reg00h–0fh.
3.1.1.16 Memory Access Mode:
Audio Processor requires a 4 K-byte PCI Memory space.
The base address (we call it
Audio MEM Base
) resides in
PCI Configuration Register 14h.
3.1.1.16.1 Memory Mapped I/O:
The 256 byte Audio IO space is mapped to 000h–0FFh of
Audio MEM space bit to bit exactly. All audio processor reg-
isters can be accessed by host in a memory cycle with ad-
dress: Audio MEM Base+offset.
3.1.1.16.2 On-chip Memory Direct R/W:
On-chip SRAM, such as ARAM, ERAM, can be accessed by
host directly (instead of index mode). The ARAM & ERAM
are mapped to 800h–FFFh.
4K-byte Memory Address Map
000h–0FFh
100h–1FFh
200h–
.
.
.
.
7FFh
800h–
.
.
.
.
FFFh
256 byte register
Reserved
Reserved
ARAM & ERAM
On-Chip ARAM, ERAM Address Map
ARAM and ERAM are mapped in range of 800h–FFFh:
800h
804h
808h
80Ch
810h
814h
818h
81Ch
820h
824h
828h
Channel 0: REG_E0h
Channel 0: REG_E4h
Channel 0: REG_E8h
Channel 0: REG_ECh
Channel 0: REG_F0h
Channel 0: REG_F4h
Channel 0: REG_F8h
Channel 0: REG_FCh
Channel 1: REG_E0h
Channel 1: REG_E4h
Channel 1: REG_E8h
82Ch
830h
834h
838h
83Ch
.
.
.
.
Channel 1: REG_ECh
Channel 1: REG_F0h
Channel 1: REG_F4h
Channel 1: REG_F8h
Channel 1: REG_FCh
.
.
.
.
3.3 AUDIO PROCESSOR REGISTER DESCRIPTIONS:
3.3.1 DMA Register:
These 16-byte registers can be accessed onAudio Base (I/O
or MEM), on DDMA Base or in DMA Snooping mode.
DMA Register Map
Name
DMAR0–3
Description
Legacy DMA Playback Buffer
Base Register
Legacy DMA Playback Byte
Count Register
Legacy DMA Playback Misc.
Register
Legacy DMA Controller
Command/Status Register
Reserved Register
Legacy DMA Single Channel
Mask Port
Legacy DMA Channel
Operation Mode Register
Legacy DMA Controller
First_Last Clear Port
Legacy DMA Controller
Master Clear Port
Legacy DMA Controller Clear
Mask Port
Legacy DMA Controller
Multi-Channel Mask Register
DMAR4–6
DMAR7
DMAR8
DMAR9
DMAR10
DMAR11
DMAR12
DMAR13
DMAR14
DMAR15
LDATA: Data bus
3.4.1.1 DMAR0 (Legacy DMA Playback Buffer Base
Register Port1)
Address:
DDMASlaveBase + 0h or AudioBase + 0h or
0000h / 0002h
Size:
8 bits
Type:
Read/Write
Default:
00h
Write: Legacy DMA Playback Buffer Base Address 7–0
Legacy DMA Playback Buffer Current Transfer Address 7–0
Read: Legacy DMA Playback Buffer Current Transfer Ad-
dress 7–0
The PCI bus interface circuit should response to I/O read to
0000h or 0002h on the PCI bus only when DMASnoopEn is
active.
www.national.com
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