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3.0 Register Description
(Continued)
Bit 7..0
X
Legacy SB16 / SBPRO Mixer
Register (indexed by SBR4) Data
Port
3.4.2.7 SBR6 (Legacy Sound Blaster ESP Reset Port)
Address:
AudioBase + 16h or AudioBase + 17h or SBBase
+ 6h or SBBase + 7h
Size:
1 bit
Type:
Write Only
Bit 0
1
Enter Legacy SB16 / SBPRO ESP
Reset State
Escape From SB16 / SBPRO ESP
Reset State
0
ESP Reset should do the following things:
Reset ESP to no operation status and clear ESP Busy Flag.
b. Stop wave engine SB channel operation.
Reset any flags that may affect the next command execu-
tion.
3.2.8 SBR7 (Legacy Sound Blaster ESP Data Port)
Address:
AudioBase + 1Ah or AudioBase + 1Bh or SBBase
+ Ah or SBBase + Bh
Size:
8 bits
Type:
Read Only
Default:
00h
Bit7..0
1
Data returned by Legacy SB16 /
SBPRO ESP Read Operation
3.4.2.9 SBR8 (Legacy Sound Blaster Command / Status
Port)
Address:
AudioBase + 1Ch orAudioBase + 1Dh or SBBase
+ Ch or SBBase + Dh
Size:
8 bits
Type:
Read/Write
Default:
00h
Write
Bit7..0
X
The Command (Operator) or Data
(Operand) Written to Legacy SB
ESP.
Read
Bit 7
0
Legacy SB ESP is Available For
Next Command / Data
Legacy SB ESP is Busy
Reserved
1
X
Bit 6..0
After the command / data has been written to the ESP Com-
mand / DATA port, bit 7 of this status register will be set to 1
(busy). After ESP has processed the written command / data
and waiting for the next one, bit 7 of this status register will
be reset to 0 (not busy). Any acknowledge byte must be
readback before any new command is issued. ESP will be
set busy after this port has ever been written and will be set
not busy if the command/status has been read four times.
3.4.2.10 SBR9 (Legacy Sound Blaster ESP Data Ready
/ IRQ Acknowledge Port 1)
Address:
AudioBase + 1Eh or SBBase + Eh
Size:
1 bit
Type:
Read Only
Default:
00h
Bit 7
0
1
X
Data is not available on SBR7
Data is available on SBR7
Reserved
Bit 6..0
Reading this register will clear the interrupt generated by the
ESP for NON-BX type legacy SB DMA command. After
SBR7 has been read, bit 7 of this register will reset to 0 (no
data) until the next read data is available and set bit 7 of this
register.
3.4.2.11 SBR10 (Legacy Sound Blaster ESP Data Ready
/ IRQ Acknowledge Port 2)
Address:
AudioBase + 1Fh or SBBase + Fh
Size:
1 bit
Type:
Read Only
Default:
00h
Bit 7
0
1
X
Data is not available on SBR7.
Data is available on SBR7.
Reserved
Bit 6..0
Reading this register will clear the interrupt generated by the
ESP for BX type legacy SB DMA command. After SBR7 has
been read, bit 7 of this register will reset to 0 (no data). If the
next read data is available at SBR7, bit 7 of this register will
again be set to 1.
3.4.3 Legacy MPU-401 Register
These 4-byte registers can be accessed on Audio Base (I/O
or MEM), or MPU401 Base.
3.4.3.1 MPUR0 (Legacy MPU-401 Data Port / IRQ
Acknowledge Port)
Address:
AudioBase + 20h or MPU401Base + 0h
Size:
8 bits
Type:
Read/Write
Default:
FEh
Read
Bit 7..0
MPU-401 Acknowledge Byte or
External MIDI Input Data in MIDI-IN
FIFO;
Write
Bit 7..0
When internal loopback mode is enabled, reading this port
will not update the MIDI-IN FIFO read counter.
MIDI Output Data
3.4.3.2 MPUR1 (Legacy MPU-401 Command / Status
Port)
Address:
AudioBase + 21h or MPU401Base + 1h
Size:
8 bits
Type:
Read/Write
Default:
80h
Read MPU-401 Status
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