參數(shù)資料
型號: LFXP20E-3FN484C
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
中文描述: FPGA, 2464 CLBS, PBGA484
封裝: 23 X 23 MM, LEAD FREE, FPBGA-484
文件頁數(shù): 69/130頁
文件大?。?/td> 1312K
代理商: LFXP20E-3FN484C
3-12
DC and Switching Characteristics
Lattice Semiconductor
LatticeXP Family Data Sheet
LVPECL
The LatticeXP devices support differential LVPECL standard. This standard is emulated using complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The LVPECL input standard is
supported by the LVDS differential input buffer. The scheme shown in Figure 3-3 is one possible solution for point-
to-point signals.
Figure 3-3. Differential LVPECL
Table 3-3. LVPECL DC Conditions
1
Over Recommended Operating Conditions
For further information on LVPECL, BLVDS and other differential interfaces please see details of additional techni-
cal documentation at the end of the data sheet.
RSDS
The LatticeXP devices support differential RSDS standard. This standard is emulated using complementary LVC-
MOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup-
ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS
standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation. Resistor values in
Figure 3-4 are industry standard values for 1% resistors.
Symbol
Description
Typical
Units
ZOUT
Output impedance
100
ohms
RP
Driver parallel resistor
187
ohms
RS
Driver series resistor
100
ohms
RT
Receiver termination
100
ohms
VOH
Output high voltage
2.03
V
VOL
Output low voltage
1.27
V
VOD
Output differential voltage
0.76
V
VCM
Output common mode voltage
1.65
V
ZBACK
Back impedance
85.7
ohms
IDC
DC output current
12.7
mA
1. For input buffer, see LVDS table.
Transmission line, Zo = 100 ohm differential
RS = 100 ohms
= 100 ohms
= 187 ohms
= 100 ohms
RS
RP
RT
Off-chip
3.3V
+
-
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