參數(shù)資料
型號(hào): LFXP20E-3FN484C
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: FPGA
中文描述: FPGA, 2464 CLBS, PBGA484
封裝: 23 X 23 MM, LEAD FREE, FPBGA-484
文件頁數(shù): 57/130頁
文件大?。?/td> 1312K
代理商: LFXP20E-3FN484C
November 2007
Data Sheet DS1001
2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
3-1
DS1001 DC and Switching_02.7
Recommended Operating Conditions
3
Absolute Maximum Ratings
1, 2, 3, 4
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions outside of those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. All chip grounds are connected together to a common package GND plane.
XPE (1.2V)
XPC (1.8V/2.5V/3.3V)
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V . . . . . . . . . . . . . . . -0.5 to 3.75V
Supply Voltage VCCP . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V . . . . . . . . . . . . . . . -0.5 to 3.75V
Supply Voltage VCCAUX . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V
Supply Voltage VCCJ . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V
Output Supply Voltage VCCIO . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V
I/O Tristate Voltage Applied
5 . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V
Dedicated Input Voltage Applied
5 . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 4.25V
Storage Temperature (Ambient) . . . . . . . . . . . . . . -65 to 150°C . . . . . . . . . . . . . . . -65 to 150°C
Junction Temp. (Tj) . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C . . . . . . . . . . . . . . . . . . . +125°C
5. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns.
Symbol
Parameter
Min.
Max.
Units
VCC
Core Supply Voltage for 1.2V Devices
1.14
1.26
V
Core Supply Voltage for 1.8V/2.5V/3.3V Devices
1.71
3.465
V
VCCP
Supply Voltage for PLL for 1.2V Devices
1.14
1.26
V
Supply Voltage for PLL for 1.8V/2.5V/3.3V Devices
1.71
3.465
V
VCCAUX
4
Auxiliary Supply Voltage
3.135
3.465
V
VCCIO
1, 2
I/O Driver Supply Voltage
1.14
3.465
V
VCCJ
1
Supply Voltage for IEEE 1149.1 Test Access Port
1.14
3.465
V
tJCOM
Junction Temperature, Commercial Operation
0
85
C
tJIND
Junction Temperature, Industrial Operation
-40
100
C
tJFLASHCOM
Junction Temperature, Flash Programming, Commercial
0
85
C
tJFLASHIND
Junction Temperature, Flash Programming, Industrial
0
85
C
1. If VCCIO or VCCJ is set to 3.3V, they must be connected to the same power supply as VCCAUX. For the XPE devices (1.2V VCC), if VCCIO or
VCCJ is set to 1.2V, they must be connected to the same power supply as VCC.
2. See recommended voltages by I/O standard in subsequent table.
3. The system designer must ensure that the FPGA design stays within the specified junction temperature and package thermal capabilities of
the device based on the expected operating frequency, activity factor and environment conditions of the system.
4. VCCAUX ramp rate must not exceed 30mV/s during power up when transitioning between 0V and 3.3V.
LatticeXP Family Data Sheet
DC and Switching Characteristics
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