參數(shù)資料
型號(hào)： LFXP20E-3FN484C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
中文描述： FPGA, 2464 CLBS, PBGA484
封裝： 23 X 23 MM, LEAD FREE, FPBGA-484
文件頁數(shù)： 36/130頁
文件大?。?/td> 1312K
代理商： LFXP20E-3FN484C
7-2
Revision History
Lattice Semiconductor
LatticeXP Family Data Sheet
September 2005
(cont.)
03.0
(cont.)
DC and Switching
Characteristics (cont.)
Updated Typical Building Block Function Performance timing numbers.
Updated External Switching Characteristics timing numbers.
Updated Internal Timing Parameters.
Updated LatticeXP Family timing adders.
Updated LatticeXP "C" Sleep Mode timing numbers.
Updated JTAG Port Timing numbers.
Pinout Information
Added clarification to SLEEPN and TOE description.
Clarification of dedicated LVDS outputs.
Supplemental
Information
Updated list of technical notes.
September 2005
03.1
Pinout Information
Power Supply and NC Connections table corrected VCCP1 pin number
for 208 PQFP.
December 2005
04.0
Introduction
Moved data sheet from Advance to Final.
Architecture
Added clarification to Typical I/O Behavior During Power-up section.
DC and Switching
Characteristics
Added clarification to Recommended Operating Conditions.
Updated timing numbers.
Pinout Information
Updated Signal Descriptions table.
Added clarification to Differential I/O Per Bank.
Updated Differential dedicated LVDS output support.
Ordering Information
Added 208 PQFP lead-free package and ordering part numbers.
February 2006
04.1
Pinout Information
Corrected description of Signal Names VREF1(x) and VREF2(x).
March 2006
04.2
DC and Switching
Characteristics
Corrected condition for IIL and IIH.
March 2006
04.3
DC and Switching
Characteristics
Added clarification to Recommended Operating Conditions for
VCCAUX.
April 2006
04.4
Pinout Information
Removed Bank designator "5" from SLEEPN/TOE ball function.
May 2006
04.5
DC and Switching
Characteristics
Added footnote 2 regarding threshold level for PROGRAMN to sysCON-
FIG Port Timing Specifications table.
June 2006
04.6
DC and Switching
Characteristics
Corrected LVDS25E Output Termination Example.
August 2006
04.7
Architecture
Added clarification to Typical I/O Behavior During Power-Up section.
Added clarification to Left and Right sysIO Buffer Pair section.
DC and Switching
Characteristics
Changes to LVDS25E Output Termination Example diagram.
December 2006
04.8
Architecture
EBR Asynchronous Reset section added.
February 2007
04.9
Architecture
Updated EBR Asynchronous Reset section.
July 2007
05.0
Introduction
Updated LatticeXP Family Selection Guide table.
Architecture
Updated Typical I/O Behavior During Power-up text section.
DC and Switching
Characteristics
Updated sysIO Single-Ended DC Electrical Characteristics table. Split
out LVCMOS 1.2 by supply voltage.
November 2007
05.1
DC and Switching
Characteristics
Added JTAG Port Timing Waveforms diagram.
Pinout Information
Added Thermal Management text section.
Supplemental
Information
Updated title list.
Date
Version
Section
Change Summary
相關(guān)PDF資料
PDF描述
LFXP20E-5FN484C
LFXP15C-4FN256C
LFZ3508VXX GENERAL PURPOSE INDUCTOR
LFZ2805HXX GENERAL PURPOSE INDUCTOR
LF02004VTX GENERAL PURPOSE INDUCTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFXP20E-3FN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7K LUTs 340 IO 1. 2V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP20E-4F256C 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7K LUTs 188 IO 1. 2V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP20E-4F256I 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7K LUTs 188 IO 1. 2V -4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP20E-4F388C 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7K LUTs 268 IO 1. 2V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP20E-4F388I 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7K LUTs 268 IO 1. 2V -4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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