- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299403 > LFXP20E-3FN484C (LATTICE SEMICONDUCTOR CORP) PDF資料下載
參數(shù)資料
| 型號： | LFXP20E-3FN484C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 中文描述： | FPGA, 2464 CLBS, PBGA484 |
| 封裝： | 23 X 23 MM, LEAD FREE, FPBGA-484 |
| 文件頁數(shù)： | 53/130頁 |
| 文件大?。?/td> | 1312K |
| 代理商： | LFXP20E-3FN484C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁當前第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁
2-26
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Table 2-9. Characteristics of Normal, Off and Sleep Modes
SLEEPN Pin Characteristics
The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the VCC supply for the
device. This pin also has a weak pull-up typically in the order of 10A along with a Schmidt trigger and glitch filter
to prevent false triggering. An external pull-up to VCC is recommended when Sleep Mode is not used to ensure the
device stays in normal operation mode. Typically the device enters Sleep Mode several hundred ns after SLEEPN
is held at a valid low and restarts normal operation as specified in the Sleep Mode Timing table. The AC and DC
specifications portion of this data sheet show a detailed timing diagram.
Configuration and Testing
The following section describes the configuration and testing features of the LatticeXP family of devices.
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeXP devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access
port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan
path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can
operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
Device Configuration
All LatticeXP devices contain two possible ports that can be used for device configuration and programming. The
test access port (TAP), which supports serial configuration, and the sysCONFIG port that supports both byte-wide
and serial configuration.
The non-volatile memory in the LatticeXP can be configured in three different modes:
In sysCONFIG mode via the sysCONFIG port. Note this can also be done in background mode.
In 1532 mode via the 1149.1 port.
In background mode via the 1149.1 port. This allows the device to be operated while reprogramming takes
place.
The SRAM configuration memory can be configured in three different ways:
At power-up via the on-chip non-volatile memory.
In 1532 mode via the 1149.1 port SRAM direct configuration.
In sysCONFIG mode via the sysCONFIG port SRAM direct configuration.
Characteristic
Normal
Off
Sleep
SLEEPN Pin
High
—
Low
Static Icc
Typical <100mA
0
Typical <100uA
I/O Leakage
<10A
<1mA
<10A
Power Supplies VCC/VCCIO/VCCAUX
Normal Range
Off
Normal Range
Logic Operation
User Defined
Non Operational
Non operational
I/O Operation
User Defined
Tri-state
JTAG and Programming circuitry
Operational
Non-operational
EBR Contents and Registers
Maintained
Non-maintained
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFXP20E-5FN484C | |
| LFXP15C-4FN256C | |
| LFZ3508VXX | GENERAL PURPOSE INDUCTOR |
| LFZ2805HXX | GENERAL PURPOSE INDUCTOR |
| LF02004VTX | GENERAL PURPOSE INDUCTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFXP20E-3FN484I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7K LUTs 340 IO 1. 2V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP20E-4F256C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7K LUTs 188 IO 1. 2V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP20E-4F256I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7K LUTs 188 IO 1. 2V -4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP20E-4F388C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7K LUTs 268 IO 1. 2V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP20E-4F388I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 19.7K LUTs 268 IO 1. 2V -4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。