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| 型號(hào)： | LFXP2-40E-6FN484I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 中文描述： | FPGA, 357 MHz, PBGA484 |
| 封裝： | 23 X 23 MM, LEAD FREE, FPBGA-484 |
| 文件頁(yè)數(shù)： | 76/92頁(yè) |
| 文件大?。?/td> | 1701K |
| 代理商： | LFXP2-40E-6FN484I |
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www.latticesemi.com
4-1
Pinout Information_01.5
June 2008
Data Sheet DS1009
2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Signal Descriptions
Signal Name
I/O
Description
General Purpose
P[Edge] [Row/Column Number*]_[A/B]
I/O
[Edge] indicates the edge of the device on which the pad is located. Valid
edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on
which the PIC exists. When Edge is T (Top) or B (Bottom), only need to spec-
ify Row Number. When Edge is L (Left) or R (Right), only need to specify Col-
umn Number.
[A/B] indicates the PIO within the PIC to which the pad is connected. Some of
these user-programmable pins are shared with special function pins. These
pins, when not used as special purpose pins, can be programmed as I/Os for
user logic. During configuration the user-programmable I/Os are tri-stated
with an internal pull-up resistor enabled. If any pin is not used (or not bonded
to a package pin), it is also tri-stated with an internal pull-up resistor enabled
after configuration.
GSRN
I
Global RESET signal (active low). Any I/O pin can be GSRN.
NC
—
No connect.
GND
—
Ground. Dedicated pins.
VCC
—
Power supply pins for core logic. Dedicated pins.
VCCAUX
—
Auxiliary power supply pin. This dedicated pin powers all the differential and
referenced input buffers.
VCCPLL
—
PLL supply pins. csBGA, PQFP and TQFP packages only.
VCCIOx
—
Dedicated power supply pins for I/O bank x.
VREF1_x, VREF2_x
—
Reference supply pins for I/O bank x. Pre-determined pins in each bank are
assigned as VREF inputs. When not used, they may be used as I/O pins.
PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
[LOC][num]_VCCPLL
—
Power supply pin for PLL: LLC, LRC, URC, ULC, num = row from center.
[LOC][num]_GPLL[T, C]_IN_A
I
General Purpose PLL (GPLL) input pads: LLC, LRC, URC, ULC, num = row
from center, T = true and C = complement, index A,B,C...at each side.
[LOC][num]_GPLL[T, C]_FB_A
I
Optional feedback GPLL input pads: LLC, LRC, URC, ULC, num = row from
center, T = true and C = complement, index A,B,C...at each side.
PCLK[T, C]_[n:0]_[3:0]
I
Primary Clock pads, T = true and C = complement, n per side, indexed by
bank and 0,1,2,3 within bank.
[LOC]DQS[num]
I
DQS input pads: T (Top), R (Right), B (Bottom), L (Left), DQS, num = ball
function number. Any pad can be configured to be output.
Test and Programming (Dedicated Pins)
TMS
I
Test Mode Select input, used to control the 1149.1 state machine. Pull-up is
enabled during configuration.
TCK
I
Test Clock input pin, used to clock the 1149.1 state machine. No pull-up
enabled.
TDI
I
Test Data in pin. Used to load data into device using 1149.1 state machine.
After power-up, this TAP port can be activated for configuration by sending
appropriate command. (Note: once a configuration port is selected it is
locked. Another configuration port cannot be selected until the power-up
sequence). Pull-up is enabled during configuration.
LatticeXP2 Family Data Sheet
Pinout Information
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFXP2-40E-6FN672C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 40KLUTs 540 I/O Inst -on DSP 1.2V -6 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP2-40E-6FN672I | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 40K LUTs 540 I/O Ins on DSP 1.2V -6 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP240E6IF484C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet |
| LFXP240E6IF484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet |
| LFXP240E6IF672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet |
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