參數(shù)資料
型號(hào)： LFXP2-40E-6FN484I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類(lèi)： FPGA
中文描述： FPGA, 357 MHz, PBGA484
封裝： 23 X 23 MM, LEAD FREE, FPBGA-484
文件頁(yè)數(shù)： 31/92頁(yè)
文件大?。?/td> 1701K
代理商： LFXP2-40E-6FN484I
2-34
Architecture
Lattice Semiconductor
LatticeXP2 Family Data Sheet
DQSXFER
LatticeXP2 devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories
that require DQS strobe be shifted 90
o. This shifted DQS strobe is generated by the DQSDEL block. The
DQSXFER signal runs the span of the data bus.
sysIO Buffer
Each I/O is associated with a exible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysIO Buffer Banks
LatticeXP2 devices have eight sysIO buffer banks for user I/Os arranged two per side. Each bank is capable of sup-
porting multiple I/O standards. Each sysIO bank has its own I/O supply voltage (VCCIO). In addition, each bank has
voltage references, VREF1 and VREF2, that allow it to be completely independent from the others. Figure 2-32
shows the eight banks and their associated supplies.
In LatticeXP2 devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are pow-
ered using VCCIO. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs inde-
pendent of VCCIO.
Each bank can support up to two separate VREF voltages, VREF1 and VREF2, that set the threshold for the refer-
enced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin.
Each I/O is individually configurable based on the bank’s supply and reference voltages.
Figure 2-32. LatticeXP2 Banks
VREF1(2)
GND
B
ank
2
V
CCIO2
VREF2(2)
VREF1(3)
GND
Ban
k
3
V
CCIO3
VREF2(3)
V
REF1(7)
GND
Ban
k
7
V
CCIO7
V
REF2(7)
V
REF1(6)
GND
Ban
k
6
V
CCIO6
V
REF2(6)
Bank 5
Bank 4
V
REF
1
(0
)
G
ND
Bank 0
V
CCI
O0
V
REF2(0)
V
RE
F1
(1
)
GND
Bank 1
V
CC
IO1
V
REF2(1
)
LEF
T
RIGHT
TOP
V
REF1(5
)
GND
V
CCIO5
V
REF
2(5
)
V
REF1(4)
GND
V
CCIO4
V
REF
2(4)
BOTTOM
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LFXP2-40E-6FN672I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 40K LUTs 540 I/O Ins on DSP 1.2V -6 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP240E6IF484C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet
LFXP240E6IF484I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet
LFXP240E6IF672C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet
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