參數(shù)資料
型號： LFXP2-40E-6FN484I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
中文描述： FPGA, 357 MHz, PBGA484
封裝： 23 X 23 MM, LEAD FREE, FPBGA-484
文件頁數(shù)： 36/92頁
文件大小： 1701K
代理商： LFXP2-40E-6FN484I
2-38
Architecture
Lattice Semiconductor
LatticeXP2 Family Data Sheet
and loaded directly onto test nodes, or test data to be captured and shifted out for veri cation. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can
operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards. For more information, please see TN1141, LatticeXP2
flexiFLASH Device Configuration
The LatticeXP2 devices combine Flash and SRAM on a single chip to provide users with flexibility in device pro-
gramming and configuration. Figure 2-33 provides an overview of the arrangement of Flash and SRAM configura-
tion cells within the device. The remainder of this section provides an overview of these capabilities. See TN1141,
LatticeXP2 sysCONFIG Usage Guide for a more detailed description.
Figure 2-33. Overview of Flash and SRAM Configuration Cells Within LatticeXP2 Devices
At power-up, or on user command, data is transferred from the on-chip Flash memory to the SRAM configuration
cells that control the operation of the device. This is done with massively parallel buses enabling the parts to oper-
ate within microseconds of the power supplies reaching valid levels; this capability is referred to as Instant-On.
The on-chip Flash enables a single-chip solution eliminating the need for external boot memory. This Flash can be
programmed through either the JTAG or Slave SPI ports of the device. The SRAM configuration space can also be
infinitely reconfigured through the JTAG and Master SPI ports. The JTAG port is IEEE 1149.1 and IEEE 1532 com-
pliant.
As described in the EBR section of the data sheet, the FlashBAK capability of the parts enables the contents of the
EBR blocks to be written back into the Flash storage area without erasing or reprogramming other aspects of the
device configuration. Serial TAG memory is also available to allow the storage of small amounts of data such as
calibration coefficients and error codes.
For applications where security is important, the lack of an external bitstream provides a solution that is inherently
more secure than SRAM only FPGAs. This is further enhanced by device locking. The device can be in one of
three modes:
EBR Blocks
Flash
Memory
EBR Blocks
SRAM
Configuration
Bits
Massively Parallel
Data Transfer
Instant-ON
Flash for
Single-Chip
Solution
FlashBAK
for EBR
Storage
Decryption
and Device
Lock
SPI and JTAG
TAG
Memory
Device Lock
for Design
Security
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFXP2-40E-6FN672C 功能描述:FPGA - 現(xiàn)場可編程門陣列 40KLUTs 540 I/O Inst -on DSP 1.2V -6 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP2-40E-6FN672I 功能描述:FPGA - 現(xiàn)場可編程門陣列 40K LUTs 540 I/O Ins on DSP 1.2V -6 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP240E6IF484C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet
LFXP240E6IF484I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet
LFXP240E6IF672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet
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