參數(shù)資料
型號(hào)： LFXP2-40E-6FN484I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
中文描述： FPGA, 357 MHz, PBGA484
封裝： 23 X 23 MM, LEAD FREE, FPBGA-484
文件頁數(shù)： 52/92頁
文件大小： 1701K
代理商： LFXP2-40E-6FN484I
3-12
DC and Switching Characteristics
Lattice Semiconductor
LatticeXP2 Family Data Sheet
RSDS
The LatticeXP2 devices support differential RSDS standard. This standard is emulated using complementary LVC-
MOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup-
ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS
standard implementation. Resistor values in Figure 3-4 are industry standard values for 1% resistors.
Figure 3-4. RSDS (Reduced Swing Differential Standard)
Table 3-4. RSDS DC Conditions
1
Over Recommended Operating Conditions
Parameter
Description
Typical
Units
VCCIO
Output Driver Supply (+/-5%)
2.50
V
ZOUT
Driver Impedance
20
RS
Driver Series Resistor (+/-1%)
294
RP
Driver Parallel Resistor (+/-1%)
121
RT
Receiver Termination (+/-1%)
100
VOH
Output High Voltage (After RP)1.35
V
VOL
Output Low Voltage (After RP)1.15
V
VOD
Output Differential Voltage (After RP)0.20
V
VCM
Output Common Mode Voltage
1.25
V
ZBACK
Back Impedance
101.5
IDC
DC Output Current
3.66
mA
1. For input buffer, see LVDS table.
RS = 294 ohms
(+/-1%)
RS = 294 ohms
(+/-1%)
RP = 121 ohms
(+/-1%)
RT = 100 ohms
(+/-1%)
On-chip
8mA
VCCIO = 2.5V
(+/-5%)
VCCIO = 2.5V
(+/-5%)
Transmission line,
Zo = 100 ohm differential
+
-
Off-chip
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