參數(shù)資料
型號： LFXP2-40E-6FN484I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
中文描述： FPGA, 357 MHz, PBGA484
封裝： 23 X 23 MM, LEAD FREE, FPBGA-484
文件頁數(shù)： 2/92頁
文件大?。?/td> 1701K
代理商： LFXP2-40E-6FN484I
2-7
Architecture
Lattice Semiconductor
LatticeXP2 Family Data Sheet
Figure 2-4. General Purpose PLL (GPLL) Diagram
Table 2-4 provides a description of the signals in the GPLL blocks.
Table 2-4. GPLL Block Signal Descriptions
Clock Dividers
LatticeXP2 devices have two clock dividers, one on the left side and one on the right side of the device. These are
intended to generate a slower-speed system clock from a high-speed edge clock. The block operates in a ÷2, ÷4 or
÷8 mode and maintains a known phase relationship between the divided down clock and the high-speed clock
based on the release of its reset signal. The clock dividers can be fed from the CLKOP output from the GPLLs or
from the Edge Clocks (ECLK). The clock divider outputs serve as primary clock sources and feed into the clock dis-
tribution network. The Reset (RST) control signal resets the input and forces all outputs to low. The RELEASE sig-
nal releases outputs to the input clock. For further information on clock dividers, please see TN1126, LatticeXP2
sysCLOCK PLL Design and Usage Guide. Figure 2-5 shows the clock divider connections.
Signal
I/O
Description
CLKI
I
Clock input from external pin or routing
CLKFB
I
PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock
(PIN or logic)
RST
I
“1” to reset PLL counters, VCO, charge pumps and M-dividers
RSTK
I
“1” to reset K-divider
DPHASE [3:0]
I
DPA Phase Adjust input
DDDUTY [3:0]
I
DPA Duty Cycle Select input
WRDEL
I
DPA Fine Delay Adjust input
CLKOS
O
PLL output clock to clock tree (phase shifted/duty cycle changed)
CLKOP
O
PLL output clock to clock tree (no phase shift)
CLKOK
O
PLL output to clock tree through secondary clock divider
CLKOK2
O
PLL output to clock tree (CLKOP divided by 3)
LOCK
O
“1” indicates PLL LOCK to CLKI
CLKFB
Divider
RST
CLKFB
CLKI
LOCK
CLKOP
CLKOS
RSTK
DPHASE
Internal Feedback
DDUTY
WRDEL
CLKOK2
CLKOK
CLKI
Divider
PFD
VCO/
LOOP FILTER
CLKOP
Divider
Phase/
Duty Cycle/
Duty Trim
CLKOK
Divider
Lock
Detect
3
相關(guān)PDF資料
PDF描述
LFXP2-17E-7F484C
LFXP20E-3FN484C
LFXP20E-5FN484C
LFXP15C-4FN256C
LFZ3508VXX GENERAL PURPOSE INDUCTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFXP2-40E-6FN672C 功能描述:FPGA - 現(xiàn)場可編程門陣列 40KLUTs 540 I/O Inst -on DSP 1.2V -6 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP2-40E-6FN672I 功能描述:FPGA - 現(xiàn)場可編程門陣列 40K LUTs 540 I/O Ins on DSP 1.2V -6 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
LFXP240E6IF484C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet
LFXP240E6IF484I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet
LFXP240E6IF672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeXP2 Family Data Sheet
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